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Numéro de référence | 74LVC373A | ||
Description | OCTAL D-TYPE LATCH | ||
Fabricant | STMicroelectronics | ||
Logo | |||
1 Page
74LVC373A
OCTAL D-TYPE LATCH
HIGH PERFORMANCE
s 5V TOLERANT INPUTS
s HIGH SPEED: tPD = 6.8ns (MAX.) at VCC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
)|IOH| = IOL = 24mA (MIN) at VCC = 3V
t(ss PCI BUS LEVELS GUARANTEED AT 24 mA
SOP
TSSOP
cs BALANCED PROPAGATION DELAYS:
utPLH ≅ tPHL
rods OPERATING VOLTAGE RANGE:
VCC(OPR) = 1.65V to 3.6V (1.2V Data
PRetention)
Table 1: Order Codes
PACKAGE
SOP
T&R
74LVC373AMTR
tes PIN AND FUNCTION COMPATIBLE WITH
le74 SERIES 373
TSSOP
74LVC373ATTR
os LATCH-UP PERFORMANCE EXCEEDS
s500mA (JESD 17)
bs ESD PERFORMANCE:
OHBM > 2000V (MIL STD 883 method 3015);
-MM > 200V
t(s)DESCRIPTION
cThe 74LVC373A is a low voltage CMOS OCTAL
uD-TYPE LATCH fabricated with sub-micron silicon
rodgate and double-layer metal wiring C2MOS
technology. It is ideal for 1.65 to 3.6 VCC
Poperations and low power and low noise
teapplications.
leThese 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
soWhile the LE inputs is held at a high level, the Q
outputs will follow the data input precisely or
inversely. When the LE is taken low, the Q outputs
will be latched precisely or inversely at the logic
level of D input data. While the (OE) input is low,
the 8 outputs will be in a normal logic state (high or
low logic level) and while high level the outputs will
be in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
It has more speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
ObFigure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 3
1/13
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Pages | Pages 13 | ||
Télécharger | [ 74LVC373A ] |
No | Description détaillée | Fabricant |
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