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PDF M48T129V Data sheet ( Hoja de datos )
| Número de pieza | M48T129V | |
| Descripción | 1Mbit (128 Kbit x 8) TIMEKEEPER SRAM | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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M48T129Y
M48T129V
5.0 or 3.3 V, 1 Mbit (128 Kbit x 8) TIMEKEEPER® SRAM
Not recommended for new design
Features
■ Integrated, ultra low power SRAM, real-time
clock, power-fail control circuit, battery, and
crystal
)■ BCD coded century, year, month, day, date,
t(shours, minutes, and seconds
c■ Battery low warning flag
du■ Automatic power-fail chip deselect and WRITE
roprotection
P■ Two WRITE protect voltages:
te(VPFD = power-fail deselect voltage)
le– M48T129Y: VCC = 4.5 to 5.5 V;
4.2 V ≤ VPFD ≤ 4.5 V
so– M48T129V: VCC = 3.0 to 3.6 V;
b2.7 V ≤ VPFD ≤ 3.0 V
O■ Conventional SRAM operation; unlimited
-WRITE cycles
t(s)■ Software controlled clock calibration for high
accuracy applications
uc■ 10 years of data retention and clock operation
din the absence of power
ro■ Self-contained battery and crystal in DIP
Ppackage
te■ Microprocessor power-on reset
le(valid even during battery backup mode)
so■ Programmable alarm output active in battery
Obbackup mode
32
1
PMDIP32 module
■ RoHS compliant
– Lead-free second level interconnect
June 2011
Doc ID 5710 Rev 5
This is information on a product still in production but not recommended for new designs.
1/28
www.st.com
1
1 page  
M48T129V, M48T129Y
1 Description
Description
The M48T129Y/V TIMEKEEPER® RAM is a 128 Kb x 8 non-volatile static RAM and real-
time clock with programmable alarms and a watchdog timer. The special DIP package
provides a fully integrated battery-backed memory and real-time clock solution. The
M48T129Y/V directly replaces industry standard 128 Kb x 8 SRAM. It also provides the non-
volatility of Flash without any requirement for special WRITE timing or limitations on the
number of WRITEs that can be performed.
The 32-pin, 600 mil DIP hybrid houses a controller chip, SRAM, quartz crystal, and a long-
life lithium button cell in a single package.
t(s)Figure 1. Logic diagram
VCC
duc17
roA0-A16
PW
teE
oleG
M48T129Y
M48T129V
8
DQ0-DQ7
RST
IRQ/FT
- ObsVSS
t(s)Table 1. Signal names
ucA0-A16
Address inputs
rodDQ0-DQ7
Data Inputs / outputs
PE Chip enable input
te G Output enable input
le W WRITE enable input
so RST
Reset output (open drain)
Ob IRQ/FT
Interrupt / frequency test output (open drain)
AI02260
VCC Supply voltage
VSS Ground
Doc ID 5710 Rev 5
5/28
5 Page 
M48T129V, M48T129Y
Operating modes
Table 4. WRITE mode AC characteristics
Symbol
Parameter(1)
M48T129Y
–70
M48T129V
–85
Unit
Min Max Min Max
tAVAV WRITE cycle time
70 85 ns
tAVWL Address valid to WRITE enable low
0
0 ns
tAVEL Address valid to chip enable low
0
0 ns
tWLWH WRITE enable pulse width
50 60 ns
tELEH Chip enable low to chip enable high
55
65 ns
duct(s) - Obsolete Product(s)2.3
Obsolete ProNote:
tWHAX
tEHAX
tDVWH
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
5
10
30
5 ns
15 ns
35 ns
tDVEH Input valid to chip enable high
30 35 ns
tWHDX
tEHDX
tWLQZ(2)(3)
tAVWH
tAVEH
tWHQX(2)(3)
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable high
WRITE enable high to output transition
5 5 ns
10 15 ns
25 30 ns
60 70 ns
60 70 ns
5 5 ns
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
2. CL = 5 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Data retention mode
With valid VCC applied, the M48T129Y/V operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting
itself when VCC falls between VPFD (max), VPFD (min) window. All outputs become high
impedance and all inputs are treated as “Don't care.”
A power failure during a WRITE cycle may corrupt data at the current addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
memory will be in a write protected state, provided the VCC fall time is not less than tF. The
M48T129Y/V may respond to transient noise spikes on VCC that cross into the deselect
window during the time the device is sampling VCC. Therefore, decoupling of the power
supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery,
preserving data and powering the clock. The internal energy source will maintain data in the
M48T129Y/V for an accumulated period of at least 10 years at room temperature. As
system power rises above VSO, the battery is disconnected, and the power supply is
switched to external VCC. Deselect continues for tREC after VCC reaches VPFD (max). For a
further more detailed review of lifetime calculations, please see application note AN1012.
Doc ID 5710 Rev 5
11/28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet M48T129V.PDF ] | |
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