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PDF CD74HC393M Data sheet ( Hoja de datos )
| Número de pieza | CD74HC393M | |
| Descripción | High Speed CMOS Logic Dual 4 -Stage Binary Counter | |
| Fabricantes | Harris Corporation | |
| Logotipo |  |
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Semiconductor
September 1997
CD74HC393,
CD74HCT393
High Speed CMOS Logic
Dual 4 -Stage Binary Counter
Features
Description
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Negative-Edge Clocking
• TTAyp=ic2a5lofCMAX = 60 MHz at VCC = 5V, CL = 15pF,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
The Harris CD74HC393 and CD74HCT393 are 4-stage
ripple-carry binary counters. Al counter stages are master-
slave flip-flops. The state of the stage advances one count
on the negative transition of each clock pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
PKG.
NO.
CD74HC393E
-55 to 125
14 Ld PDIP E14.3
CD74HCT393E
-55 to 125
14 Ld PDIP E14.3
CD74HC393M
-55 to 125
14 Ld SOIC M14.15
CD74HCT393M
-55 to 125
14 Ld SOIC M14.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all elec-
trical specifications. Please contact your local sales office or
Harris customer service for ordering information.
Pinout
CD74HC393, CD74HCT393
(PDIP, SOIC)
TOP VIEW
1CP 1
1MR 2
1Q0 3
1Q1 4
1Q2 5
1Q3 6
GND 7
14 VCC
13 2CP
12 2MR
11 2Q0
10 2Q1
9 2Q2
8 2Q3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
1
File Number 1653.1
1 page  
CD74HC393, CD74HCT393
DC Electrical Specifications (Continued)
PARAMETER
HCT TYPES
SYMBOL
TEST
CONDITIONS
VI (V) IO (mA)
VCC
(V)
25oC
-40oC TO 85oC -55oC TO 125oC
MIN TYP MAX MIN MAX MIN MAX UNITS
High Level Input
Voltage
VIH -
-
4.5 to
2
-
-
2
-
2
-
V
5.5
Low Level Input
Voltage
VIL
-
-
4.5 to
-
- 0.8 - 0.8 -
0.8 V
5.5
High Level Output
Voltage
CMOS Loads
VOH VIH or VIL -0.02 4.5 4.4 -
- 4.4 - 4.4
-
V
High Level Output
Voltage
TTL Loads
-4
4.5 3.98 -
- 3.84 -
3.7
-
V
Low Level Output
Voltage
CMOS Loads
VOL VIH or VIL 0.02
4.5
-
- 0.1 - 0.1 -
0.1 V
Low Level Output
Voltage
TTL Loads
4
4.5 -
- 0.26 - 0.33 -
0.4 V
Input Leakage
Current
II
VCC and
0
5.5 -
- ±0.1 -
±1
-
±1 µA
GND
Quiescent Device
Current
ICC VCC or 0
GND
5.5 -
-8
- 80
- 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC
VCC
-2.1
-
4.5 to
-
100 360
-
450
-
490 µA
5.5
NOTE: For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
nCP 0.4
nMR
1
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
Prerequisite for Switching Specifications
PARAMETER
HC TYPES
Maximum Clock
Frequency
Clock Pulse Width
Reset Recovery Time
SYMBOL VCC (V) MIN
fMAX
tW
tREC
26
4.5 30
6 35
2 80
4.5 16
6 14
25
4.5 5
65
25oC
TYP
MAX
-40oC TO 85oC
MIN MAX
-55oC TO 125oC
MIN MAX
UNITS
- - 5 - 4 - ns
- - 24 - 20 - ns
- - 28 - 24 - ns
-
- 100 - 120 -
ns
- - 20 - 24 - ns
- - 17 - 20 - ns
- - 5 - 5 - ns
- - 5 - 5 - ns
- - 5 - 5 - ns
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet CD74HC393M.PDF ] | |
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