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PDF NCP51403 Data sheet ( Hoja de datos )
| Número de pieza | NCP51403 | |
| Descripción | Termination Regulator | |
| Fabricantes | ON Semiconductor | |
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Hay una vista previa y un enlace de descarga de NCP51403 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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NCP51403
3 Amp VTT Termination
Regulator DDR1, DDR2,
DDR3, LPDDR3, DDR4
The NCP51403 is a source/sink Double Data Rate (DDR)
termination regulator specifically designed for low input voltage and
low−noise systems where space is a key consideration.
The NCP51403 maintains a fast transient response and only requires
a minimum output capacitance of 20 mF. The NCP51403 supports a
remote sensing function and all power requirements for DDR VTT bus
termination. The NCP51403 can also be used in low−power chipsets
and graphics processor cores that require dynamically adjustable
output voltages.
The NCP51403 is available in the thermally−efficient DFN10
Exposed Pad package, and is rated both Green and Pb−free.
Features
• Input Voltage Rails: Supports 2.5 V, 3.3 V and 5 V Rails
• PVCC Voltage Range: 1.1 to 3.5 V
• Integrated Power MOSFETs
• Phase Margin >45° with Recommended 20 mF VTT Capacitance
• PGOOD − Logic output pin to Monitor VTT Regulation
• EN − Logic input pin for Shutdown mode
• VRI − Reference Input Allows for Flexible Input Tracking Either
Directly or Through Resistor Divider
• Remote Sensing (VTTS)
• Built−in Under Voltage Lockout and Over Current Limit
• Thermal Shutdown
• Small, Low−Profile 10−pin, 3x3 DFN Package
• These Devices are Pb−Free and are RoHS Compliant
Applications
• DDR Memory Termination
• Desktop PC’s, Notebooks, and Workstations
• Servers and Networking equipment
• Telecom/Datacom, GSM Base Station
• Graphics Processor Core Supplies
• Set Top Boxes, LCD−TV/PDP−TV, Copier/Printers
• Chipset/RAM Supplies as Low as 0.5 V
• Active Bus Termination
www.onsemi.com
DFN10, 3x3, 0.5P
CASE 506CL
MARKING DIAGRAM
51403
ALYWG
G
51403
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTION
VRI
PVCC
VTT
PGND
VTTS
+
1
2
3
4
5
GND
10 VCC
9 PGOOD
8 GND
7 EN
6 VRO
Exposed Pad
ORDERING INFORMATION
Device
Package Shipping†
NCP51403MNTXG DFN10 3000 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
(see notes on page 6)
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 1
1
Publication Order Number:
NCP51403/D
1 page  
NCP51403
General
The NCP51403 is a sink/source tracking termination
regulator specifically designed for low input voltage and
low external component count systems where space is a key
application parameter. The NCP51403 integrates a
high−performance, low−dropout (LDO) linear regulator
that is capable of both sourcing and sinking current. The
LDO regulator employs a fast feedback loop so that small
ceramic capacitors can be used to support the fast load
transient response. To achieve tight regulation with
minimum effect of trace resistance, a remote sensing
terminal, VTTS, should be connected to the positive terminal
of the output capacitors as a separate trace from the high
current path from VTT.
VRI − Generation of Internal Voltage Reference
The output voltage, VTT, is regulated to VRO. When VRI
is configured for standard DDR termination applications,
VRI can be set by an external equivalent ratio voltage divider
connected to the memory supply bus (VDDQ). The
NCP51403 supports VRI voltage from 0.5 V to 1.8 V,
making it versatile and ideal for many types of low−power
LDO applications.
VRO − Reference Output
When it is configured for DDR termination applications,
VRO generates the DDR VTT reference voltage for the
memory application. It is capable of supporting both a
sourcing and sinking load of 10 mA. VRO becomes active
when VRI voltage rises to 435 mV and VCC is above the
UVLO threshold. When VRO is less than 360 mV, it is
disabled and subsequently discharges to GND through an
internal 10 kW MOSFET. VRO is independent of the EN pin
state.
EN − Enable Control
When EN is driven high, the NCP51403 VTT regulator
begins normal operation. When EN is driven low, VTT is
discharges to GND through an internal 18−W MOSFET.
VREF remains on when EN is driven low.
PGOOD − PowerGood
The NCP51403 provides an open−drain PGOOD output
that goes high when the VTT output is within ±20% of VRO.
PGOOD de−asserts within 10 ms after the output exceeds the
limits of the PowerGood window. During initial VTT
startup, PGOOD asserts high 2 ms after the VTT enters power
good window. Because PGOOD is an open−drain output, a
100 kW, pull−up resistor between PGOOD and a stable active
supply voltage rail is required.
The LDO has a constant over−current limit (OCL). Note
that the OCL level reduces by one−half when the output
voltage is not within the power good window. This reduction
is non−latch protection. For VCC under−voltage lockout
(UVLO) protection, the NCP51403 monitors VCC voltage.
When the VCC voltage is lower than the UVLO threshold
voltage, both the VTT and VRO regulators are powered off.
This shutdown is also non−latch protection.
Thermal Shutdown with Hysteresis
If the NCP51403 is to operate in elevated temperatures for
long durations, care should be taken to ensure that the
maximum operating junction temperature is not exceeded.
To guarantee safe operation, the NCP51403 provides
on−chip thermal shutdown protection. When the chip
junction temperature exceeds 150°C, the part will shutdown.
When the junction temperature falls back to 125°C, the
device resumes normal operation. If the junction
temperature exceeds the thermal shutdown threshold then
the VTT and VRO regulators are both shut off, discharged by
the internal discharge MOSFETs. The shutdown is a
non−latch protection.
Tracking Startup and Shutdown
The NCP51403 also supports tracking startup and
shutdown when EN is tied directly to the system bus and not
used to turn on or turn off the device. During tracking
startup, VTT follows VRO once VRI voltage is greater than
435 mV. VRI follows the rise of VDDQ memory supply rail
via a voltage divider. PGOOD is asserted 2 ms after VTT is
within ±20% of VRO. During tracking shutdown, VTT falls
following VRO until VRO reaches 360 mV. Once VRO falls
below 360 mV, the internal discharge MOSFETs are turned
on and quickly discharge both VRO and VTT to GND. PGOOD
is de−asserted once VTT is beyond the ±20% range of VRO.
www.onsemi.com
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet NCP51403.PDF ] | |
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