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GSI Technology - 9Mb Pipelined and Flow Through Synchronous NBT SRAM

Numéro de référence GS881Z36AT
Description 9Mb Pipelined and Flow Through Synchronous NBT SRAM
Fabricant GSI Technology 
Logo GSI Technology 





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GS881Z36AT fiche technique
GS881Z18/36AT-250/225/200/166/150/133
100-Pin TQFP
Commercial Temp
Industrial Temp
9Mb Pipelined and Flow Through
Synchronous NBT SRAM
250 MHz133 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
• Fully pin-compatible with both pipelined and flow through
NtRAM™, NoBL™ and ZBT™ SRAMs
• IEEE 1149.1 JTAG-compatible Boundary Scan
• On-chip write parity checking; even or odd selectable
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
Functional Description
The GS881Z18/36AT is a 9Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS881Z18/36AT may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS881Z18/36AT is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
Parameter Synopsis
-250 -225 -200 -166 -150 -133 Unit
Pipeline tKQ 2.5 2.7 3.0 3.4 3.8 4.0 ns
3-1-1-1 tCycle 4.0 4.4 5.0 6.0 6.7 7.5 ns
3.3 V
Curr (x18) 280 255 230 200 185 165 mA
Curr (x36) 330 300 270 230 215 190 mA
2.5 V
Curr (x18) 275 250 230 195 180 165 mA
Curr (x36) 320 295 265 225 210 185 mA
Flow
Through
2-1-1-1
tKQ
tCycle
5.5 6.0 6.5 7.0 7.5 8.5 ns
5.5 6.0 6.5 7.0 7.5 8.5 ns
3.3 V
Curr (x18) 175 165 160 150 145 135 mA
Curr (x36) 200 190 180 170 165 150 mA
2.5 V
Curr (x18) 175 165 160 150 145 135 mA
Curr (x36) 200 190 180 170 165 150 mA
Rev: 1.03 11/2004
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology

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