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GS8320Z36T Datasheet دیتاشیت PDF دانلود

دیتاشیت - GSI Technology - 36Mb Pipelined and Flow Through Synchronous NBT SRAM

شماره قطعه GS8320Z36T
شرح مفصل 36Mb Pipelined and Flow Through Synchronous NBT SRAM
تولید کننده GSI Technology 
آرم GSI Technology 


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GS8320Z36T شرح
100-Pin TQFP
Commercial Temp
Industrial Temp
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GS8320Z18/36T-250/225/200/166/150/133
36Mb Pipelined and Flow Through 250 MHz133 MHz
Synchronous NBT SRAM
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
Functional Description
• NBT (No Bus Turn Around) functionality allows zero wait
The GS8320Z18/36T is a 36Mbit Synchronous Static SRAM.
read-write-read bus utilization; Fully pin-compatible with
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
both pipelined and flow through NtRAM™, NoBL™ and
pipelined read/double late write or flow through read/single
ZBT™ SRAMs
late write SRAMs, allow utilization of all available bus
• 2.5 V or 3.3 V +10%/5% core power supply
bandwidth by eliminating the need to insert deselect cycles
• 2.5 V or 3.3 V I/O supply
when the device is switched from read to write cycles.
• User-configurable Pipeline and Flow Through mode
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 100-lead TQFP package
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
-250 -225 -200 -166 -150 -133 Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.3 2.5 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.6 7.5 ns
3.3 V
Curr (x18) 365 335 300 265 240 220 mA
Curr (x32/x36) 430 390 350 305 280 245 mA
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8320Z18/36T may be configured by the user to operate
2.5 V
Curr (x18) 360 330 295 260 235 215 mA
Curr (x32/x36) 420 380 340 295 270 235 mA
Flow
Through
2-1-1-1
tKQ
tCycle
6.0 6.5 7.5 8.5 10 11 ns
7.0 7.5 8.5 10 10 15 ns
3.3 V
Curr (x18) 200 200 180 180 180 135 mA
Curr (x32/x36) 230 230 195 195 195 145 mA
2.5 V
Curr (x18) 200 200 180 180 180 130 mA
Curr (x32/x36) 225 225 195 195 195 145 mA
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8320Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 100-pin TQFP package.
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
A
BC
DE
F
Read/Write
R
WR
W
R
W
Flow Through
Data I/O
Pipelined
Data I/O
QA DB QC DD QE
QA DB QC DD QE
Rev: 1.01 10/2001
1/25
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.

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