PDF XRS10L140 Data sheet ( Hoja de datos )

Número de pieza	XRS10L140
Descripción	SERIAL ATA II: 1:4 PORT MULTIPLIER
Fabricantes	Exar Corporation
Logotipo
Hay una vista previa y un enlace de descarga de XRS10L140 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! PRELIMINARY XRS10L140 SERIAL ATA II: 1:4 PORT MULTIPLIER JUNE 2006 REV. P1.0.2 1.0 INTRODUCTION The EXAR XRS10L140 is a Serial ATA port multiplier designed for next generation enterprise class disk array systems that use SATA mid-planes. The device is targeted at low cost storage applications. This function is used when one active host has to communicate with multiple SATA drives. The XRS10L140 supports up to 4 SATA drives and utilizes the full bandwidth of the host connection. The upstream ports of XRS10L140 can also be attached to a port selector (XRS10L20) or a Serial ATA Switch to provide redundancy in a more complex topology. The XRS10L140 includes enhanced features such as staggered HDD spin-up, power management control, hot plug capability and support for legacy software. The XRS10L140 acts as a retimer, maintaining independent signaling domains between the drives themselves and the external interconnect. The high-speed serial input features selectable equalization adjustment and the high-speed serial output features selectable pre-emphasis to compensate for ISI (Inter-Symbol Interference) and increase maximum cable distances. XRS10L140 meets tight jitter budgets in SATA applications. Exar's serial I/O technology enables reliable data transmission over 1 meter or more of FR-4 and 15 meters or more of unequalized copper cable. Host and drive port speeds can be mixed and matched, based upon inherent data rate negotiation present in the SATA II specifications. The MDIO bus allows simple configuration of the device. To summarize, the XRT10L24 port multiplier device allows the system designer to increase the number of serial ATA connections in an enclosure that does not have a sufficient number of serial ATA connections for all of the drives in the enclosure. OVERVIEW OF PORT MULTIPLIER LOGIC XRS10L140 port multiplier is a multiplexer where one active host connection is multiplexed to multiple device connections. The XRS10L140 is an extensible design that can support up to 4 device connections and utilizes the full bandwidth of the host connection. XRS10L140 uses four bits, known as the PM Port field in all Serial ATA frame types, to route frames between the selected host and the appropriate device. PM ports 0 through 3 are valid device ports within the 4-output XRS10L140, while PM port 15 is designated for communication between the host and the XRS10L140 itself. For host-to-device transactions, the PM Port field is designated by the host in order to specify which device the frame is intended for. For device-to-host transactions, the XRS10L140 fills in the PM Port field with the port address of the device that is transmitting the frame. STANDARDS COMPLIANCE The XRS10L140 is compliant with the following industry specifications: • Serial ATA, Revision 1.0a • Serial ATA II: Extensions to Serial ATA 1.0a, Revision 1.2 • Serial ATA II PHY Electrical Specifications, Revision 1.0 • Serial ATA II: Port Multiplier, Revision 1.2 APPLICATIONS • Serial ATA Enclosures • Other Serial ATA link replicator applications • Buffers for externally connected links • High density storage boxes • RAID Subsystems FEATURES GENERAL FEATURES • Five independent 3/1.5G SATA ports. • Supports 3/1.5G rate detection/speed negotiation. • Supports power down modes - Active, partial, slumber and power down. PORT MULTIPLIER LOGIC FEATURES • Low latency architecture. • Supports OOB signaling for SATA applications. Internal OOB detectors for COMSAS, COMRESET/ COMINIT and COMWAKE. TEST AND CONTROL FEATURES • Supports MDIO Bus. • Outputs for various failure modes. • Built-In self test mode through the MDIO bus. • Supports various loopback modes. Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com 1 page PRELIMINARY XRS10L140 REV. P1.0.2 SERIAL ATA II: 1:4 PORT MULTIPLIER 3.0 FUNCTIONAL DESCRIPTION A top-level view of the XRS10L140 is shown in Figure 2 outlining the interfaces to the device and the required support components. The data path can be seen at the top of the device. This includes the output transmit and input receive path at the top left, providing the upstream interface to the host, and the four output transmit and input receive paths at the top right, providing the downstream interface to the target devices. The clocking, control, and configuration interfaces are shown below the dotted line. FIGURE 2. XRS10L140 INTERFACES Serial ATA Upstream Interface to HBAs SiT_P0/SiT_N0 SOT_P/N[3:0] SiR_P0/SiR_N0 SOR_P/N[3:0] Serial ATA Downstream Interface to HBAs Control and configuration Interface DRACT[3:0] HBACT0 RESETB PWRDNB MDC MDIO1 VDDA RBIAS Calibration Resistor 49.9 Ω ± 5% CMU_REF_P/N XOD XOG TCK TDI TDO1 TMS TRST Reference Clock Crystal Oscillator Inputs JTAG Interface The XRS10L140 incorporates identical instantiations of a dual-channel Serial ATA II 3 Gbps PHY macro. This common building block provides a uniform implementation with common characteristics and a common register map, but provides a functional implementation of independent PHY blocks. Digital logic implementations of Serial ATA link layer blocks along with port multiplier logic provide the remainder of the data path within the XRS10L140. In addition, management and control interfaces including an MDIO interface for register control, a JTAG interface for boundary scan purposes, and a resistor calibration circuit complete the device. A block diagram of the XRS10L140 is shown in Figure 3. FIGURE 3. XRS10L140 BLOCK DIAGRAM SIR 0 S IT0 S ATA II 3G PHY SATA II L IN K LAYER RATE ADJUST F IF O S ATA II LIN K LAYER S ATA II LIN K LAYER PORT M ULTIP LIER S ATA II LIN K LAYER S ATA II LIN K LAYER SA TA II 3G PHY SA TA II 3G PHY SA TA II 3G PHY SA TA II 3G PHY SOT0 SOR0 SOT1 SOR1 SOT2 SOR2 SOT3 SOR3 5 5 Page PRELIMINARY XRS10L140 REV. P1.0.2 SERIAL ATA II: 1:4 PORT MULTIPLIER 3.7 Test and Loopback Modes The XRS10L140 provides for loopback testing on both the host and device interfaces, and incorporates a number of internal testing features, as outlined in the following subsections. 3.7.1 Host Side Loopback Modes The XRS10L140 supports two forms of host loopback modes: a shallow serial loopback implemented within the host PHY macro, or a deep parallel loopback implemented within the device PHY macros after the port selector and port multiplier functionality. SHALLOW HOST LOOPBACK MODE The shallow host loopback mode is shown in Figure 9. In this mode, the incoming data stream from the host and embedded clock are recovered by an internal CDR, and the deserialized data is retransmitted serially back to the host, as clocked by the recovered clock. In this implementation, the received data is still transmitted to the internal port selector block and will propagate through to the device side output pins. FIGURE 9. SHALLOW HOST LOOPBACK MODE SiT0 SiR0 PHY Layer Port Multiplier Dual PHY Dual PHY SOT0 SOR0 SOT1 SOR1 SOT2 SOR2 SOT3 SOR3 DEEP HOST LOOPBACK MODE The deep host loopback mode is shown in Figure 10. In this mode, the incoming data stream from the host is transmitted through the digital blocks within the XRS10L140, and the loopback path is implemented at the device-side Serial ATA PHY block. Note that once again, the looped back data is still transmitted on the device- side output pins. The deep host loopback mode is enabled by using the Parallel Loopback registers for the downstream PHYs in Device 2 or 3. This received data must be in the form of valid SATA frames for a deep loopback to be successful, or the internal logic must be bypassed via MDIO register settings. FIGURE 10. DEEP HOST LOOPBACK MODE SiT0 SiR0 PHY Layer Port Multiplier Dual PHY Dual PHY SOT0 SOR0 SOT1 SOR1 SOT2 SOR2 SOT3 SOR3 11 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet XRS10L140.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
XRS10L140	SERIAL ATA II: 1:4 PORT MULTIPLIER	Exar Corporation

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar