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PDF UT04VS50P Data sheet ( Hoja de datos )
| Número de pieza | UT04VS50P | |
| Descripción | Voltage Supervisor | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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Standard Products
UT04VS50P Voltage Supervisor
Data Sheet
July 28, 2014
www.aeroflex.com/VoltSupv
FEATURES
4.5V to 5.5V Operating voltage range
6 Fixed Threshold Voltage Monitors (3.3V, 2.5V, 1.8V, 1.5V,
1.2V, 1.0V)
Fixed & Adjustable Threshold Voltage Select modes
Threshold Voltage Select with TH0, TH1 pins
Adjustable RESET Timeout with external capacitor
Independent Voltage Monitoring and Sequencing
Manual Reset Input Pin
Active Low and Active High RESET pins
Output Voltages Open Drain
Two VOUTS active high and two VOUTS programmable
with INV Pin
RESET, RESETB Outputs Open Drain
Over-voltage Detection Mode
Operating Temperature Range -55oC to +125oC
Low Power Typical 1000A
Tolerance Select Input Pin (5% & 10%)
RESET, RESETB, VOUT1, VOUT2, VOUT3 and VOUT4
guaranteed to be in the correct state for VDD down to 1.2V
Packaging options:
- 28-lead ceramic dual flatpack
Operational environment:
- Total dose: 300 krad(Si)
- SEL Immune: <110 MeV-cm2/mg @125oC
- SET Immune: <109MeV-cm2/mg
Standard Microelectronics Drawing (SMD) 5962-13206
- QML Q and V
INTRODUCTION
The UT04VS50P is a radiation-hardened Voltage Supervisor
which simultaneously monitors up to four supply levels utilized
in a system, providing status output for each signal, VOUTx, as
well as system reset signal if any of the monitored signals moves
out of range. To set the monitor trip points, the TH0 and TH1
pins allow the selection of three sets of preset threshold levels
per channel, determined by an internal bandgap voltage
reference, to reduce supply and temperature variance. A fourth
selection allows the user to determine the level for each channel.
There are two modes of operation, determined by the OVSH pin.
In the first mode, when the OVSH pin is connected to VSS, four
independent supplies are monitored for an under-voltage
condition. In the second mode when the OVSH pin is connected
to VDD, under-voltage and over-voltage of the inputs are
monitored. In this mode, two supplies can be monitored using
channels 1 and 3 or channels 2 and 4, respectively. For flexibility,
both system RESET and RESETB outputs are available for
interfacing to the system. Each channel has an enable, ENx,
allowing use of one, two, three or all four monitor channels.
This device includes a 3V regulator that supplies power to the
internal circuitry. The margin (or tolerance) to the given threshold
voltage, for under-voltage monitoring, is determined by the
setting of the TOL pin. The logic sense of the channel 3 and 4
outputs can be inverted by setting the INV pin, appropriately.
Also, MRB, master reset, provides a means for a manual input
to activate the RESET signals. In addition, the user can adjust
two timing parameters by the addition of external capacitors to
the device. These are the response times of the channel VOUTx
signal when the associated input returns to a valid level,
implemented by a capacitor connected to CDLYx and the time
to clear RESET (and RESETB) when a channel enable or input
level becomes valid; implemented by CRESET.
APPLICATION
The UT04VS50P supervisory circuit reduces the complexity and
number of circuits required to monitor power supply and battery
functions in microprocessor, DSP, microcontroller, ASIC and
FPGA systems. The UT04VS50P supervisory circuit
significantly improves system reliability and accuracy over
comparable systems that use separate ICs or discrete
components.
1
1 page  
Number
24
25
26
27
28
Pins
CDLY3
VOUT3
CDLY1
VOUT1
VDD
Type
Description
Analog Output
External capacitor delay connection. Allows adjustment of the
VOUT3 timing after VIN3 becomes valid when OVSH=0. See
Functional Descriptions - CDLY timing section.
Open Drain Digital
Output
Output of VIN3 monitor when OVSH=0; inactive when OVSH=1.
With INV=0, logic 1 indicates that the VIN3 input is at a valid level.
With INV=1, logic 0 indicates that VIN3 is at a valid level. Device
contains active pull-down device; requires external pull-up.
Analog Output
External capacitor delay connection. Allows adjustment of the
VOUT1 timing after VIN1 becomes valid. See Functional
Descriptions - CDLY timing section.
Open Drain Digital
Output
When OVSH=0, it indicates the signal state of the VIN1 monitor.
When OVSH=1, it indicates the combined signal states for VIN1 and
VIN3 (under-voltage and over-voltage detection). See Functional
Descriptions - Thresholds, Device contains active pull-down device;
requires external pull-up.
Supply
Supply voltage, 4.5 to 5.5V.
5
5 Page 
Note: The maximum level at any analog channel input is limit-
ed to 3.6V. This limits the maximum voltage level of the mon-
itored signal. When the device is placed in the adjustable
threshold state (TH0 = TH1 = logic 1) utilizing an external re-
sistive divider, the maximum voltage of the monitored signal
can be greater than the maximum level when using the preset
threshold, as given by:
Vmonitor < [(RT + RB)/RB] * VRFTH
where RT is the top resistor of the divider and RB is the lower
resistor, tied to VSS. One should account for resistor toleranc-
es. Also, with the resistive divider tied to VSS, the minimum
voltage that can be monitored is VRFTH. It is possible to tie the
resistive divider to the VDD supply and, hence, monitor signals
lower than VRFTH. If this arrangement is used, the variation in
the VDD supply will affect the result.
Enables
Each channel has an enable, ENx. When a channel is disabled
its corresponding output is held in the logic 0 state. Also, the
outputs are not affected by any changes of signals that may oc-
cur on disabled channels. However, when a channel is enabled,
the outputs are put into the mode for the length of time as deter-
mined by RESET timeout. As noted, when the OVSH is logic
1, the enables of channels 1 and 3 are connected together to af-
fect channel 1 output and those for channels 2 and 4 affect chan-
nel 2 output. See Figure 4 for timing. The condition whereby all
four enables are in the logic 0 state is reserved and should not
be used.
Master Reset
The device has a master reset (inverted logic) input, MRB,
which provides a means for the system reset to be combined
with the voltage supervisor reset functionality. The timing of
this input with respect to the RESET/RESETB outputs is shown
in Figure 5. Timing specifications are given in the AC Charac-
teristics table. An RC time constant can be associated with this
pin to extend the RESET state.
Timing (CDLY, CRESET)
Many of the timing parameters of the device are fixed and listed
in the AC Characteristics table. Along with those are the default
value for the CDLY function, response time of VOUTx after
the corresponding input signal becomes valid, and the C func-
tion, defining the timeout until an output is released after an
event (an ENx or all enabled VOUTx becoming valid).
CDLY timing
The delay time (tDELAY+) for each channel is independently ad-
justable by adding a capacitor to the desired CDLYx pin. The
equation that defines the delay is:
tDELAY+ = (Cdly + 18pF) * (VTH_CDLY)/ ICH_CDLY
where Cdly is the user chosen, external capacitance connected
to CDLY pin, 18pF is the internal capacitance (any significant
board capacitance should be added), ICH_CDLY is the charging
current with value given in the DC Characteristics table and
VTH_CDLY is the threshold voltage utilized by this function,
also given in the DC Characteristics table. Note that maximum
delay times in this equation are calculated using the minimum
charging current and maximum VTH voltage. Minimum delays
in the equation are calculated using maximum charging current
and minimum VTH voltage.
CRESET timing
The timeout for the outputs (tRP), when activated by changes of
an ENx or VINx signal, is adjustable by the addition of an ex-
ternal capacitor to the CRESET pin. The equation that defines
the RESET timeout period is:
tRP=(Creset+ 40pF)*(VTH_CRESET) /ICH_RESET
where Creset is the user chosen, external capacitance, 40pF is
the device default and parasitic capacitance (any significant
board capacitance should be added), ICH_RESET is the charging
current with value given in the DC Characteristics table and
VTH_CRESET is the threshold voltage utilized by this function,
also given in the DC Characteristics table. Note that maximum
delay times in this equation are calculated using the minimum
charging current and maximum VTH voltage. Minimum delays
in the equation are calculated using maximum charging current
and minimum VTH voltage.
Output drive (open drain - power, speed)
The outputs from the device, RESET, RESETB and VOUTx
are of the open drain type, having only an active pulldown, with
characteristics given in the DC and AC Characteristics tables.
Hence, the user must supply an appropriate valued resistor for
the pullup. Note: This allows for 1) the connecting of several
outputs from the given device or other devices and 2) provides
for voltage drive-level adjustment by connecting the resistor to
an appropriate supply (note the voltage level is constrained by
the operating voltage of this device, VDD).
INV function
For further system interface flexibility, the INV pin provides
for the logical inversion of the channel 3 and 4 VOUT signals.
In all modes, the logic level of the output is inverted from its
normal state.
11
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| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet UT04VS50P.PDF ] | |
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