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PDF RDC5028C Data sheet ( Hoja de datos )
| Número de pieza | RDC5028C | |
| Descripción | 16-Bit Monolithic Tracking Standard Products Rad Tolerant Resolver-To-Digital Converter | |
| Fabricantes | Aeroflex Circuit Technology | |
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Standard Products
Datasheet
RDC5028C 16-Bit Monolithic Tracking
Rad Tolerant Resolver-To-Digital Converter
www.aeroflex.com/RDC
May 7, 2014
FEATURES
Enhanced version of the ACT5028B
Radiation performance
- Total dose: 1 Mrad(Si), Dose rate = 50 - 300 rads(Si)/s
- SEL:Immune up to 100 MeV-cm2/mg
+5VDC power only
Programmable: By using a few non critical external resistors and capacitors
- Resolution: 10, 12, 14 or 16 bit resolution
- Bandwidth
- Tracking rate
Low power: +5V @ 20 mA typ
45 to 30,000 Hz carrier frequency range
Accuracy:
- 10.0 Arc Minutes if not compensated by INL correction factors.
- 5.3 Arc Minutes using INL correction factors.
Differential instrument amplifiers resolver input
-55° to +125°C operating temperature
Digital interface logic voltage of 3.3V to 5V
Designed for aerospace and high reliability space applications
Packaging – Hermetic
- 52 Pin Ceramic QUAD flat package (CQFP), .956" SQ x .100"Ht
- Weight: 5.0g max
Evaluation board available for test and evaluation. See Aeroflex Application note AN5028-1
Aeroflex Plainview’s Radiation Hardness Assurance Plan is DLA Certified to MIL-PRF-38534, Appendix G.
APPLICATIONS
This single chip Resolver-to-Digital Converter (RDC) is used in shaft angle control systems, and is suitable for space
or other radiation environments that require > 1 Mrad(Si) total dose tolerance. The part is latchup free in heavy ion
environments (e.g., geosynchronous orbits) and is estimated to experience SEU induced errors of less than 15 minutes
of arc at a rate of 1 per device per 2 years when operating dynamically.
THEORY OF OPERATION
The RDC5028 converter is a single CMOS Type II tracking resolver to digital converter monolithic chip. It is
implemented using precision analog circuitry and digital logic. For flexibility, the converter bandwidth, dynamics and
velocity scaling are externally set with passive components. Refer to Figure 1, RDC5028 Block Diagram.
The converter is powered from +5VDC. Analog signals are referenced to signal ground, which is nominally VCC/2.
The converter consists of three main sections; the Analog Control Transformer (CT), the Analog Error Processor (EP)
and the Digital Logic Interface.
The CT has two analog resolver inputs (Sin and Cos) that are buffered by high impedance input instrumentation type
amplifiers and the 16 bit digital word which represents the output digital angle. The CT performs the ratiometric
trigonometric computation of:
SIN(A) sin(wt) COS(B) – COS(A) sin(wt) SIN(B) = SIN(A-B) sin(wt)
Utilizing amplifiers, switches, logic and resistors in precision ratios. “A” represents the resolver angle, “B“ represents
the digital angle and sin(wt) represents the resolver reference carrier frequency.
The Error Processor is configured as a critically damped Type II loop. The AC error, SIN (A-B) sin (wt) is full wave
demodulated using the reference squared off as its drive. This DC error is integrated in an analog integrator yielding a
velocity voltage which in turn drives a Voltage Controlled Oscillator (VCO). Note in the block diagram, hysterisis is
added to prevent dithering and disables counting when the error is less than 1 LSB. This VCO is an incremental
integrator (constant voltage input to position rate output) which, together with the velocity integrator, forms a Type II
loop. A lead is inserted to stabilize the loop and a lag is inserted at a higher frequency to attenuate the carrier
frequency ripple. The error processor drives the 16 bit digital output until it nulls out. Then angle “A” = “B”. The
digital output equals angle input to the accuracy of the precision control transformer. The various error processor
settings are done with external resistors and capacitors so that the converter loop dynamics can be easily controlled by
the user.The digital logic interface has a separate power line, VLI/O that sets the interface logic 1 level. It can be set
anywhere from +3V to the +5V power supply.
SCD5028-2 Rev G
1 page  
ELECTRICAL CHARACTERISTICS 2/, 5/, 6/
(TA = -55°C to +125°C)
PARAMETER
16 Bit Mode 3/
VCO Frequency 3/
CONDITIONS
MIN
TYP
1 1 B1 - B16
16 -
1.05 -
ELECTRICAL SPECIFICATIONS 2/, 5/, 6/
(TA = -55°C to +125°C)
ANALOG SIGNAL INPUTS
SIN, COS, REF, VCOIN,
INTIN1, INTIN2,
BPF1, BPF2
SYM
VSIN,
VCOS,
VREF
FREF
PARAMETER
Voltage measurement made
between ± inputs 9/
Frequency 1/
DC Resistance 3/
Capacitance 3/
DC Bias on -Sin, -Cos 3/
Bias Current 3/
+25°C
+125°C
MIN
1.0
45
2.5
-
-
-100
-1000
MAX
-
-
UNITS
RPS
MHz
TYP
1.3
MAX UNITS
1.5 VRMS
-
-
5
VCC / 2
30K
-
15
-
Hz
M
pF
VDC
- +100 nA
- +1000 nA
DIGITAL INPUTS
ENABLE, DATALOAD
SC2, SC1,
INH 3/
VIL Logic Low
VIH Logic High
IIN Leakage Current
+25°C
+125°C
DC Resistance
Capacitance
-
2
-200
-2000
2.5
-
- 0.8 VDC
- - VDC
- +200 nA
- +2000 nA
- - M
5 15 pF
DIGITAL OUTPUTS
BUSY, RIPPLE
CW/CCW 3/
VOL Logic Low @ 1.6mA
VOH Logic High @ -1.6mA
-
VLI/O - 0.8
-
-
0.3 VDC
- VDC
DIGITAL I/O
B1 - B16 7/ 3/
SCD5028-2 Rev G 5/7/2014
VIL Logic Low
- - 0.8 VDC
VIH Logic High
2 - - VDC
VOL Logic Low @ 1.6mA
- - 0.3 VDC
VOH Logic High @ -1.6mA
VLI/O - 0.8 -
- VDC
IIN Leakage Current
+25°C
-200 - +200 nA
+125°C
-2000
- +2000 nA
IZ High-Z Leakage Current
+25°C
-200 - +200 nA
+125°C
-2000
- +2000 nA
5 Aeroflex Plainview
5 Page 
REFERENCE CONDITIONING
Most resolvers have a LEADING input to output phase shift. A simple C-R leading phase shift network
(Figure 5 – Reference Conditioning) from the resolver reference to the RDC’s reference input will provide
the compensating phase shift required to bring the signals in phase. If the resolver has a LAGGING input to
output phase shift an R-C lagging phase shift network (low pass network) would be required.
Note the C-R phase lead circuit on the input to the Demodulator (BPF1 and BPF2) in Figure 1 should be
considered when calculating the total system phase compensation.
The formula for calculating the phase shift network is as follows:
1
Phase angle = ArcTan 6.28 x (R7 + R8) x C
FREF
Select a convenient capacitor value and perform the following calculation to determine the proper resistor
value.
R= 1
(Tan (Phase Angle)) x FREF x 6.28 x C
POWER UP INITIALIZATION
The RDC5028 RDC converter can provide incorrect data output if a unit step of 180° (starting at any
angle) is introduced to the Sin / Cos input.
This is difficult to reproduce since a Resolver will never provide a unit step function to the RDC chip.
The only time this would be a concern is during power up, if the Resolver is set to 180°. The RDC will
initialize its internal counter to 0000h which simulates the unit step function mentioned above. In
practice this error condition during power up is difficult to produce because of the dynamics associated
with all the variables when power is first applied.
If the system designer does nothing to accommodate this potential problem the system could see an
error at power on, however, this error will be self corrected once the Resolver begins to rotate. If the
Resolver does not rotate, the error can be corrected by writing to the RDC5028 any angle except 180°.
VELOCITY CONTROL
The RDC5028 RDC exhibits nonlinearity below 4 degrees/sec due to an anti-dither circuit that was
added to reduce the effects of any noise condition that may exist. This result can be seen in the least
significant bit or on the velocity output pins 9 & 10 on this device.
SCD5028-2 Rev G 5/7/2014
11
Aeroflex Plainview
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet RDC5028C.PDF ] | |
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