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PDF PE97632DIE Data sheet ( Hoja de datos )
| Número de pieza | PE97632DIE | |
| Descripción | Fractional-N Frequency Synthesizer | |
| Fabricantes | Peregrine Semiconductor | |
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Product Description
Peregrine’s PE97632 is a high performance fractional-N PLL
capable of frequency synthesis up to 3.5 GHz. The device is
designed for superior phase noise performance while
providing an order of magnitude reduction in current
consumption, when compared with the existing commercial
space PLLs.
The PE97632 features a 10/11 dual modulus prescaler,
counters, a delta sigma modulator and a phase comparator
as shown in Figure 1. Counter values are programmable
through either a serial interface or directly hard-wired.
The PE97632 is optimized for commercial space
applications. Single event latch-up (SEL) is physically
impossible. Fabricated in Peregrine’s patented UltraCMOS®
technology, the PE97632 offers excellent RF performance
and intrinsic radiation tolerance.
Product Specification
PE97632 DIE
3.5 GHz Delta-Sigma Modulated
Fractional-N Frequency Synthesizer
for Low Phase Noise Applications
Features
3.5 GHz operation
÷10/11 dual modulus prescaler
Phase detector output
Serial or direct mode access
Frequency selectivity: comparison
frequency / 218
Low power: –35 mA @ 3.3V
Radiation tolerant
Ultra-low phase noise
Pin compatible with the PE9763
(reference application note AN24 at
www.psemi.com)
Figure 1. Block Diagram
Document No. DOC-01626-3 │ www.psemi.com
©2008-2015 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 16
1 page  
PE97632 DIE
Product Specification
Table 2. Absolute Maximum Ratings
Symbol
VDD
VI
II
IO
TSTG
Parameter/Condition
Supply voltage
Voltage on any input
DC into any input
DC into any output
Storage temperature range
Min Max Unit
–0.3 4.0
V
–0.3 VDD + 0.3 V
–10 +10 mA
–10 +10 mA
–65 +150 °C
Table 3. Operating Ratings
Symbol
VDD
TA
Parameter/Condition
Supply voltage
Operating ambient
temperature range
Min Max
2.85 3.45
–40 +85
Unit
V
°C
Table 4. ESD Ratings
Symbol
Parameter/Condition
Level Unit
VESD
ESD Voltage Human Body Model on
all pins except pin 52 (Note 1)
ESD Voltage Human Body Model on
pin 60 (Notes 1 and 2)
1000
300
V
V
Notes: 1. Periodically sampled, not 100% tested. Tested per MIL-STD-883,
M3015 C2.
2. Pin 60 is a test pin only. It is not used in normal operation.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 4.
Latch-Up Immunity
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
ELDRS
UltraCMOS devices do not include bipolar minority
carrier elements and; therefore, do not exhibit en-
hanced low-dose-rate sensitivity.
Document No. DOC-01626-3 │ www.psemi.com
©2008-2015 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 16
5 Page 
PE97632 DIE
Product Specification
Figure 4. Serial Interface Mode Timing Diagram
Sdata
E_WR
Sclk
tEC
S_WR
tDSU
tDHLD
tClkH
tClkL
tCE
tCWR
tPW tWRC
Enhancement Register
The functions of the enhancement register bits are shown below with all bits active “high”.
Table 10. Enhancement Register Bit Functionality
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit Function
Reserve*
Reserve*
fp output
Power down
Counter load
MSEL output
fc output
LD disable
Description
Reserved.
Reserved.
Drives the M counter output onto the DOUT output.
Power down of all functions except programming interface.
Immediate and continuous load of counter programming.
Drives the internal dual modulus prescaler modulus select (MSEL) onto the DOUT output.
Drives the reference counter output onto the DOUT output.
Disables the LD pin for quieter operation.
Note: * Program to 0.
Document No. DOC-01626-3 │ www.psemi.com
©2008-2015 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 16
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| PDF Descargar | [ Datasheet PE97632DIE.PDF ] | |
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