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PDF PE97240 Data sheet ( Hoja de datos )
| Número de pieza | PE97240 | |
| Descripción | Integer-N Frequency Synthesizer | |
| Fabricantes | Peregrine Semiconductor | |
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Product Description
Peregrine’s PE97240 is a radiation tolerant high-
performance Integer-N PLL capable of frequency
synthesis up to 5 GHz. The device is designed for
commercial space applications and optimized for
superior phase noise performance.
The PE97240 features a selectable prescaler
modulus of 5/6 or 10/11, counters and a phase
comparator as shown in Figure 1. Counter values are
programmable through either a serial interface or
directly hard-wired.
The PE97240 is available in a 44-lead CQFP and is
manufactured on Peregrine’s UltraCMOS® process, a
patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering excellent
RF performance and intrinsic radiation tolerance.
Figure 1. Functional Diagram
Product Specification
PE97240
Radiation Tolerant UltraCMOS®
Integer-N Frequency Synthesizer
for Low Phase Noise Applications
Features
Frequency range
5 GHz in 10/11 prescaler modulus
4 GHz in 5/6 prescaler modulus
Phase noise floor figure of merit:
–230 dBc/Hz
Low power: 75 mA @ 2.7V
Serial or direct mode access
Packaged in a 44-lead CQFP
100 kRad(Si) total dose
PE97240
Document No. DOC-15214-7 │ www.e2v-us.com
©2010-2015 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 21
1 page  
PE97240
Product Specification
Table 5. DC Characteristics @ VDD = 2.7V, –40 °C < TA < +85 °C, unless otherwise specified
Symbol
Parameter
Condition
Min Typ Max
Prescaler disabled,
fC = 50 MHz, FIN = 500 MHz
VDD = 2.6–2.8V
5/6 prescaler,
IDD
Operational supply current
fC = 50 MHz, FIN = 3 GHz
VDD = 2.6–2.8V
10/11 prescaler,
fC = 50 MHz, FIN = 3 GHz
VDD = 2.6–2.8V
34 50
72 105
74 110
Digital Inputs: All except FR, FIN, FIN
VIH High level input voltage
VIL Low level input voltage
IIH High level input current
IIL Low level input current
Reference Divider input: FR
IIHR High level input current
IILR Low level input current
Counter and phase detector outputs: PD_D, PD_U
VOLD
Output voltage LOW
VOHD
Output voltage HIGH
Lock detect outputs: CEXT, LD
VOLC
Output voltage LOW, CEXT
VOHC
Output voltage HIGH, CEXT
VOLLD
Output voltage LOW, LD
VDD = 2.6–2.8V
VDD = 2.6–2.8V
VIH = VDD = 2.8V
VIL = 0, VDD = 2.8V
VIH = VDD = 2.8V
VIL = 0, VDD = 2.8V
Iout = 6 mA
Iout = –3 mA
Iout = 100 μA
Iout = –100 μA
Iout = 1 mA
0.7 x VDD
–10
–300
VDD – 0.4
VDD – 0.4
0.3 x VDD
70
300
0.4
0.4
0.4
Unit
mA
mA
mA
V
V
μA
μA
μA
μA
V
V
V
V
V
Document No. DOC-15214-7 │ www.e2v-us.com
©2010-2015 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 21
5 Page 
PE97240
Product Specification
Typical Performance Data @ VDD = 2.6–2.8V, –40 °C < TA < +85 °C, fC = 50 MHz and FIN = 3 GHz
Figure 10. FOM vs. Reference Power and Temp
(5/6 Prescaler, VDD = 2.7V)
‐220
Figure 11. FOM vs. Reference Power and Temp
(10/11 Prescaler, VDD = 2.7V)
‐220
‐230 ‐230
‐240
‐250
‐260
Floor FOM, ‐40°C
Floor FOM, +25°C
Floor FOM, +85°C
Flicker FOM, ‐40°C
Flicker FOM, +25°C
Flicker FOM, +85°C
‐240
‐250
‐260
Floor FOM, ‐40°C
Floor FOM, +25°C
Floor FOM, +85°C
Flicker FOM, ‐40°C
Flicker FOM, +25°C
Flicker FOM, +85°C
‐270 ‐270
‐280
‐5
025
Reference Power (dBm)
8
Figure 12. FOM vs. Temp and Supply Voltage
(5/6 Prescaler, PF_IN = 2 dBm)
‐220
‐280
‐5
025
Reference Power (dBm)
8
Figure 13. FOM vs. Temp and Supply Voltage
(10/11 Prescaler, PF_IN = 2 dBm)
‐220
‐230
‐240
‐250
‐260
Floor FOM, 2.6V
Floor FOM, 2.7V
Floor FOM, 2.8V
Flicker FOM, 2.6V
Flicker FOM, 2.7V
Flicker FOM, 2.8V
‐270
‐280
‐40
25
Temperature (°C)
85
FFigiguur0ere1140. .(R5(RF5/F6/6SPSePrenernsessiscticitavialvieltieyrty,rv,VvsVDs.DD.FD=FIN=IN2a2.a6n.6nVdVd)T*)T*eemmpp
‐230
‐240
‐250
‐260
Floor FOM, 2.6V
Floor FOM, 2.7V
Floor FOM, 2.8V
Flicker FOM, 2.6V
Flicker FOM, 2.7V
Flicker FOM, 2.8V
‐270
‐280
‐40
25
Temperature (°C)
85
Figure
Figure
0
15.
11.
((RR11FF00//SS11ee11nnPPssrriieettiissvvcciittaayylleevvrrss,, ..VVFFDDIIDDNN
and Temp
=an2d.6TVe)*mp
= 2.6V)*
‐5 ‐5
‐40 C
‐40 C
‐10
+25 C ‐10
+25 C
+85 C
+85 C
‐15 ‐15
‐20 ‐20
‐25 ‐25
‐30 ‐30
Operating Frequency (MHz)
Operating Frequency (MHz)
Note: * RF sensitivity is the minimum input power level required for the PLL to maintain lock. Operating at these levels does not guarantee the SSB phase noise
performance in Table 6.
Document No. DOC-15214-7 │ www.e2v-us.com
©2010-2015 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 21
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet PE97240.PDF ] | |
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