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Aeroflex Circuit Technology - 16 Megabit RadTolerant SRAM MCM

Numéro de référence UT8Q512K32E
Description 16 Megabit RadTolerant SRAM MCM
Fabricant Aeroflex Circuit Technology 
Logo Aeroflex Circuit Technology 





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UT8Q512K32E fiche technique
Standard Products
UT8Q512K32E 16 Megabit RadTolerant SRAM MCM
Data Sheet
June 28, 2011
FEATURES
25ns maximum (3.3 volt supply) address access time
MCM contains four (4) 512Kx8 industry-standard
asynchronous SRAMs; the control architecture allows
operation as 8, 16, 24 or 32-bit data width
TTL compatible inputs and output levels, three-state
bidirectional data bus
Typical radiation performance
- Total dose: 50krads
- SEL Immune >110 MeV-cm2/mg
- SEU LETTH(0.25) = >52 MeV-cm2/mg
- Saturated Cross Section , 2.8E-8 cm2/bit
- <1.1E-9 errors/bit-day, Adams 90% geosynchronous
heavy ion
Packaging:
- 68-lead dual cavity ceramic quad flatpack (CQFP)
(11.0 grams)
INTRODUCTION
The UT8Q512K32E RadTolerant product is a high-performance
2M byte (16Mbit) CMOS static RAM multi-chip module
(MCM), organized as four individual 524,288 x 8 bit SRAMs
with a common output enable. Memory expansion is provided
by an active LOW chip enable (En), an active LOW output
enable (G), and three-state drivers. This device has a power-
down feature that reduces power consumption by more than 90%
when deselected.
Writing to each memory is accomplished by taking chip enable
(En) input LOW and write enable (Wn) inputs LOW. Data on
the eight I/O pins (DQ0 through DQ7) is then written into the
location specified on the address pins (A0 through A18). Reading
from the device is accomplished by taking chip enable (En) and
output enable (G) LOW while forcing write enable (Wn) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
Standard Microcircuit Drawing 5962-01533
- QML Q and Vcompliant part
W3
E3
The input/output pins are placed in a high impedance state when
the device is deselected (En HIGH), the outputs are disabled (G
HIGH), or during a write operation (En LOW and Wn LOW).
Perform 8, 16, 24 or 32 bit accesses by making Wn along with
En a common input to any combination of the discrete memory
die.
W2
E2
W1
E1
W0
E0
A(18:0)
G
512K x 8
512K x 8
512K x 8
512K x 8
DQ(31:24)
or
DQ3(7:0)
DQ(23:16)
or
DQ2(7:0)
DQ(15:8)
or
DQ1(7:0)
Figure 1. UT8Q512K32E SRAM Block Diagram
DQ(7:0)
or
DQ0(7:0)
1

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