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Aeroflex Circuit Technology - Monolithic 16M SRAM

Numéro de référence UT8ER512K32
Description Monolithic 16M SRAM
Fabricant Aeroflex Circuit Technology 
Logo Aeroflex Circuit Technology 





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UT8ER512K32 fiche technique
Standard Products
UT8ER512K32 Monolithic 16M SRAM
Data Sheet
July 24, 2012
www.aeroflex.com/memories
FEATURES
20ns Read, 10ns Write maximum access times
Functionally compatible with traditional 512K x 32 SRAM
devices
CMOS compatible input and output levels, three-state
bidirectional data bus
- I/O Voltage 3.3 volt, 1.8 volt core
Operational environment:
- Total-dose: 100 krad(Si)
- SEL Immune: <111MeV-cm2/mg
- SEU error rate = 8.1x10-16 errors/bit-day assuming
geosynchronous orbit, Adam’s 90% worst environment,
and 6600ns default Scrub Rate Period (=97% SRAM
availability)
Packaging options:
- 68-lead ceramic quad flatpack (6.898 grams)
Standard Microcircuit Drawing 5962-06261
- QML Q & V
INTRODUCTION
The UT8ER512K32 is a high-performance CMOS static RAM
organized as 524,288 words by 32 bits. Easy memory expansion
is provided by active LOW and HIGH chip enables (E1, E2), an
active LOW output enable (G), and three-state drivers. This
device has a power-down feature that reduces power
consumption by more than 90% when deselected.
Writing to the device is accomplished by driving chip enable one
(E1) input LOW, chip enable two (E2) HIGH and write enable
(W) input LOW. Data on the 32 I/O pins (DQ0 through DQ31)
is then written into the location specified on the address pins (A0
through A18). Reading from the device is accomplished by
taking chip enable one (E1) and output enable (G) LOW while
forcing write enable (W) and chip enable two (E2) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins will appear on the I/O pins.
The 32 input/output pins (DQ0 through DQ31) are placed in a
high impedance state when the device is deselected (E1 HIGH
or E2 LOW), the outputs are disabled (G HIGH), or during a
write operation (E1 LOW, E2 HIGH and W LOW).
A0
A1
W
A2
E1
Pre-Charge Circuit
A3
E2 A4
Memory Array
A5 512K x 32
A6
A7
A8
A9
A17
G A18
I/O Circuit
Column Select
DQ(31) to DQ(0)
Read/Write
Circuit
Data Control
EDAC
A10 A11 A12 A13 A14 A15 A16
BUSY, SCRUB
MBE
Figure 1. UT8ER512K32 SRAM Block Diagram
1

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