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PDF UT54ACS299E Data sheet ( Hoja de datos )
| Número de pieza | UT54ACS299E | |
| Descripción | CMOS 8-bit Universal Shift/Storage Register | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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Standard Products
UT54ACS299E
CMOS 8-bit Universal Shift/Storage Register with Three-State Outputs
Datasheet
July 2, 2013
www.aeroflex.com/Logic
FEATURES
Common parallel I/O for reduced pin count
Additional serial inputs and outputs for expansion
Three-state outputs for bus-oriented applications
Operate with outputs enabled or at high impedance
Four operating modes: shift left, shift right, load and store
Can be cascaded for n-bit word lengths
0.6m Commercial RadHardTM CMOS
- Total dose: 100K rad(Si)
- Single Event Latchup immune
- SEU Onset LET: 95 MeV-cm2/mg (4.5V) and
48MeV-cm2/mg (3.0V)
Applications:
- Stacked or push-down registers
- Buffer storage
- Accumulator registers
Output source/sink 24mA
Available QML Q or V processes
Standard Microcircuit Drawing 5962-06238
Package:
- 20-lead flatpack
DESCRIPTION
The UT54ACS299E 8-bit shift/storage register is built using
Aeroflex’s Commercial RadHardTM epitaxial CMOS technolo-
gy and is ideal for space applications. The UT54ACS299E is an
8-bit universal shift/storage register featuring multiplexed I/O
ports to achieve full 8-bit data handling in a single 20-pin pack-
age. Two function-select (S0, S1) inputs and two output enable
(OE1, OE2) inputs can be used to choose the mode of operation
listed in the function table. Additional outputs are provided for
flip flops Q0, Q7 to allow easy serial cascading. A separate
active low master reset (MR) is used to reset the register, over-
riding the select and CP inputs. All flip-flops are brought out
through three-state buffers to separate I/O pins that also serve
as data inputs in the parallel load mode. All other state changes
are initiated by the rising edge of the clock.
LOGIC SYMBOL
MR (9)
OE1 (2)
OE2 (3)
S0 (1)
S1 (19)
CP (12)
R SRG8
& 3EN13
0
1
M
0
3
C4/1 /2
DS0 (11)
I00 (7)
I01 (13)
I02 (6)
I03 (14)
I04 (5)
I05 (15)
I06 (4)
I07 (16)
DS7 (18)
1, 4D
3, 4D
5, 13
3, 4D
6, 13
Z5
Z6
(8)
Q0
3, 4D
12, 13
2, 4D
Z12
(17)
Q7
PIN DESCRIPTION
Pin Names
Description
CP Clock Pulse Input
DS0 Serial Data Input for Right Shift
DS7 Serial Data Input for Left Shift
S0, S1 Mode Select Inputs
MR Asynchronous Master Reset
OE1, OE2 Three-State Output Enable Inputs
IO0-IO7 Parallel Data Inputs or Three-State Parallel Out-
puts
Q0, Q7 Serial Outputs
1
1 page  
DC ELECTRICAL CHARACTERISTICS 1
( -55C < TC < +125C)
SYMBOL
PARAMETER
VIL Low level input voltage2
VIH High level input voltage2
IIN Input leakage current
IOZ Three-state output leakage current
IOS Short-circuit output current 4, 5
VOL1 Low-level output voltage 6
VOL2 Low-level output voltage 6
VOL3 Low-level output voltage6, 7
VOH1 High-level output voltage6
VOH2 High-level output voltage6
CONDITION
MIN
VDD from 3.0V to 5.5V
VDD from 3.0V to 5.5V
0.7 VDD
VDD from 3.0V to 5.5V
VIN = VDD or VSS
-1
VDD from 3.0V to 5.5V
VIN = VDD or VSS
-10
VO = VDD or VSS
VDD from 3.0V to 5.5V
-600
IOL = 12mA
IOL = 100A
VDD = 3.0V to 3.6V
VIN = 0.7VDD or 0.3VDD
IOL= 24mA
-55C, 25C
IOL= 24mA
+125C
IOL= 100A
VDD = 4.5V to 5.5V
VIN = 0.7VDD or 0.3VDD
IOL= 50mA
-55C, 25C
VDD = 5.5V
+125C
VIN = 0.7VDD or 0.3VDD
IOH = -12mA
IOH = -100A
VDD = 3.0V to 3.6V
VIN = 0.7VDD or 0.3VDD
VDD - 0.6
VDD - 0.2
IOH= -24mA
-55C, 25C
IOH= -24mA
+125C
IOH= -100A
VDD = 4.5V to 5.5V
VIN = 0.7VDD or 0.3VDD
VDD - 0.64
VDD - 0.8
VDD - 0.2
MAX
0.3 VDD
1
10
600
0.4
0.2
0.36
0.5
0.2
0.8
1.0
UNIT
V
V
A
A
mA
V
V
V
V
V
5
5 Page 
Propagation Delay
CP
Output
tPLH1,2
Enable Disable Times
OEn
5V Output
Normally Low
5V Output
Normally High
tPZL
tPZH
VDD/2-0.2
VDD/2+0.2
Setup and Hold Measurements
Sn or DSn or IOn
CP Input
tS1,2,3
tH1,2,3
MR
Data Outputs
Q0, Q7, IO<0:7>
tW2
tREC
tW1
tPHL3
tPHL4
tPHL1,2
VDD
VDD/2
0V
VOH
VDD/2
VOL
tPLZ
.2VDD + .2V
tPHZ
.8VDD - .2V
VDD
VDD/2
0V
VDD/2
.2VDD
.8VDD
VDD/2
VDD
VDD/2
0.0V
VDD
VDD/2
0.0V
VDD
VDD/2
0.0V
VOH
VDD/2
VOL
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet UT54ACS299E.PDF ] | |
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