PDF GS9091B Data sheet ( Hoja de datos )

Número de pieza	GS9091B
Descripción	270Mb/s Deserializer
Fabricantes	Gennum
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GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Key Features • SMPTE 259M-C compliant descrambling and NRZI to NRZ decoding (with bypass) • DVB-ASI 8b/10b decoding • Integrated Cable Equalizer • 500m typical equalization of Belden 1694A cable • Integrated line-based FIFO for data alignment/delay, clock phase interchange, DVB-ASI data packet extraction and clock rate interchange, and ancillary data packet extraction • Integrated VCO and reclocker • User selectable additional processing features including: TRS, ANC data checksum, and EDH CRC error detection and correction programmable ANC data detection illegal code remapping • Internal flywheel for noise immune H, V, F extraction • Automatic standards detection and indication • Enhanced Gennum Serial Peripheral Interface (GSPI) • JTAG test interface • Polarity insensitive for DVB-ASI and SMPTE signals • +1.8V core power supply with optional +1.8V or +3.3V I/O power supply • Small footprint (11mm x 11mm) • Low power operation (typically 350mW) • Pb-free and RoHS compliant Applications • SMPTE 259M-C Serial Digital Interfaces • DVB-ASI Serial Digital Interfaces Description The GS9091B is a 270Mb/s equalizing and reclocking dese- rializer with an internal FIFO. It provides a complete re- ceive solution for SD-SDI and DVB-ASI applications. In addition to equalizing, reclocking and deserializing the input data stream, the GS9091B performs NRZI -to-NRZ de- coding, descrambling as per SMPTE 259M-C, and word alignment when operating in SMPTE mode. When operat- ing in DVB-ASI mode, the device will word align the data to K28.5 sync characters and 8b/10b decode the received stream. The integrated equalizer is optimized for 270Mb/s and can typically equalize up to 500m of Belden 1694A cable. Both the equalizer and the internal reclocker are fully compati- ble with both SMPTE and DVB-ASI input streams. The GS9091B includes a range of data processing functions such as EDH support (error detection and handling), and automatic standards detection. The device can also detect and extract SMPTE 352M payload identifier packets and in- dependently identify the received video standard. This in- formation is read from internal registers via the host interface port. The GS9091B also incorporates a video line-based FIFO. This FIFO may be used in four user-selectable modes to car- ry out tasks such as data alignment / delay, clock phase in- terchange, MPEG packet extraction and clock rate interchange, and ancillary data packet extraction. Parallel data outputs are provided in 10-bit multiplexed format, with the associated parallel clock output signal op- erating at 27MHz. The device may also be used in a low-latency data pass through mode where only descrambling and word align- ment will be performed in SMPTE mode. GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI www.gennum.com Data Sheet 38910 - 2 July 2008 1 of 71 Proprietary & Confidential 1 page 1. Pin Out 1.1 Pin Assignment 1 2 3 4 5 6 7 8 9 10 A LF+ NC LB_ CONT VCO_ VDD VBG FIFO_EN AUTO/ LOCKED PCLK DOUT9 MAN B LF- PLL_ VDD PLL_ GND VCO_ GND NC FW_EN CORE _VDD SMPTE_ DVB_ASI DOUT8 BYPASS C ANA_ VDD ANA_ VDD NC NC NC NC NC IO_VDD NC DOUT7 D ANA_ GND ANA_ GND NC CORE _GND CORE IO_GND IO_GND _GND NC NC DOUT6 E EQ_GND TERM NC CORE CORE IO_GND IO_GND _GND _GND NC IO_VDD DOUT5 HEAT_ F SDI SINK_ GND HEAT_ G SDI SINK_ GND HEAT_ H EQ_VDD SINK_ GND HEAT_ SINK_ GND CORE _GND HEAT_ SINK_ GND CORE _GND HEAT_ SINK_ GND NC CORE IO_GND IO_GND NC IO_VDD DOUT4 _GND CORE IO_GND IO_GND NC _GND NC DOUT3 NC NC NC IO_VDD RD_ DOUT2 RESET J AGC+ EQ_ JTAG_EN BYPASS CS_ TMS SDOUT CORE DATA_ _TDO _VDD ERROR STAT2 STAT3 DOUT1 K AGC- NC IOPROC SCLK _EN RESET _TCK SDIN _TDI STAT0 STAT1 RD_CLK DOUT0 Figure 1-1: Pin Assignment GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 5 of 71 Proprietary & Confidential 5 Page Table 1-1: Ball List and Description (Continued) Ball Name K6 SDIN_TDI K7, K8, J8, J9 STAT[0:3] K9 RD_CLK Timing Type Description Synchronous with SCLK_TCK Synchronous with PCLK or RD_CLK – Input Output Input CONTROL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Serial Data Input / Test Data Input Host Mode (JTAG_EN = LOW): SDIN_TDI operates as the host interface serial input, SDIN, used to write address and configuration information to the internal registers of the device. JTAG Test Mode (JTAG_EN = HIGH): SDIN_TDI operates as the JTAG test data input, TDI. MULTI FUNCTION I/O PORT Signal levels are LVCMOS / LVTTL compatible. Programmable multi-function outputs. By programming the bits is the IO_CONFIG register, each pin can output one of the following signals: •H •V •F • FIFO_LD • ANC • EDH_DETECT • FIFO_FULL • FIFO_EMPTY These pins are set to certain default values depending on the configuration of the device and the internal FIFO mode selected. See Section 3.12 for details. FIFO READ CLOCK Signal levels are LVCMOS / LVTTL compatible. The application layer clocks the parallel data out of the FIFO on the rising edge of RD_CLK. GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 11 of 71 Proprietary & Confidential 11 Page

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