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PDF UT54ACS193 Data sheet ( Hoja de datos )
| Número de pieza | UT54ACS193 | |
| Descripción | Synchronous 4-Bit Up-Down Dual Clock Counters | |
| Fabricantes | Aeroflex Circuit Technology | |
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Standard Products
UT54ACS193/UT54ACTS193
Synchronous 4-Bit Up-Down Dual Clock Counters
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
Look-ahead circuitry enhances cascaded counters
Fully synchronous in count modes
Parallel asynchronous load for modulo-N count lengths
Asynchronous clear
1.2μ CMOS (ACTS193) and .6μm CRH CMOS process
(ACS193)
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
UT54ACS193 - SMD 5962-96566
UT54ACTS193 - SMD 5962-96567
DESCRIPTION
The UT54ACS193 and the UT54ACTS193 are synchronous 4-
bit, binary reversible up-down binary counters. Synchronous
operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with each
other when instructed. Synchronous operation eliminates the
output counting spikes normally associated with asynchronous
counters.
The outputs of the four flip-flops are triggered on a low-to-high-
level transition of either count input (Up or Down). The direc-
tion of the counting is determined by which count input is pulsed
while the other count input is high.
The counters are fully programmable. The outputs may be preset
to either level by placing a low on the load input and entering
the desired data at the data inputs. The output will change to
agree with the data inputs independently of the count pulses.
Asynchronous loading allows the counters to be used as modulo-
N dividers by simply modifying the count length with the preset
inputs.
A clear input has been provided that forces all outputs to the low
level when a high level is applied. The clear function is inde-
pendent of the count and the load inputs.
The counter is designed for efficient cascading without the need
for external circuitry. The borrow output (BO) produces a low-
level pulse while the count is zero and the down input is low.
Similarly, the carry output (CO) produces a low-level pulse
while the count is maximum
PINOUTS
16-Pin DIP
Top View
B
QB
QA
DOWN
UP
QC
QD
VSS
B 1 16 VDD
QB 2 15 A
QA 3 14 CLR
DOWN 4 13 BO
UP 5 12 CO
QC 6 11 LOAD
QD 7 10 C
VSS 8
9D
16-Lead Flatpack
Top View
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
A
CLR
BO
CO
LOAD
C
D
FUNCTION TABLE
FUNCTION
CLOCK
UP
Count Up
↑
Count Down
H
Reset
X
Load Preset
Input
X
CLOCK
DOWN
H
↑
X
X
CLR
L
L
H
L
LOAD
H
H
X
L
1
1 page  
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All ACTS specifications are valid for radiation dose ≤ 1E6 rads(Si) and all ACS specifications are valid for radiation dose ≤ 5E5 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
5
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| PDF Descargar | [ Datasheet UT54ACS193.PDF ] | |
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