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PDF DS2482-100 Data sheet ( Hoja de datos )
| Número de pieza | DS2482-100 | |
| Descripción | Single-Channel 1-Wire Master | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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DS2482-100
Single-Channel 1-Wire Master
General Description
The DS2482-100 is an I2C-to-1-Wire® bridge device
that interfaces directly to standard (100kHz max) or fast
(400kHz max) I2C masters to perform bidirectional pro-
tocol conversion between the I2C master and any
downstream 1-Wire slave devices. Relative to any
attached 1-Wire slave device, the DS2482-100 is a
1-Wire master. Internal, factory-trimmed timers relieve
the system host processor from generating time-critical
1-Wire waveforms, supporting both standard and over-
drive 1-Wire communication speeds. To optimize
1-Wire waveform generation, the DS2482-100 performs
slew-rate control on rising and falling 1-Wire edges and
provides additional programmable features to match
drive characteristics to the 1-Wire slave environment.
Programmable, strong pullup features support 1-Wire
power delivery to 1-Wire devices such as EEPROMs
and sensors. The DS2482-100 combines these features
with an output to control an external MOSFET for
enhanced strong pullup application. The I2C slave
address assignment is controlled by two binary
address inputs, resolving potential conflicts with other
I2C slave devices in the system.
Applications
Printers
Medical Instruments
Industrial Sensors
Cell Phones, PDAs
Benefits and Features
• Allows Easy Interface Between a I2C Microport and a
1-Wire Slave
• I2C Host Interface Supports 100kHz and 400kHz
I2C Communication Speeds
• 1-Wire Master IO with Selectable Active or Passive
1-Wire Pullup
• Provides Reset/Presence, 8-Bit, Single-Bit, and
3-Bit 1-Wire IO Sequences
• Standard and Overdrive 1-Wire Communication
Speeds
• Two Address Inputs for I2C Address Assignment
• Minimizes Line Noise Reducing System EMI
• Slew-Controlled 1-Wire Edges
• Supports EEPROMs, Temperature Sensors, or Other
1-Wire Slaves That Have Momentary High Source
Current Modes
• Strong 1-Wire Pullup Provided by an Internal Low-
Impedance Signal Path
• PCTLZ Output to Optionally Control an External
MOSFET for Stronger Pullup Requirements
• Operating Range: 2.9V to 5.5V, -40°C to +85°C
• 8-Pin (150 mils) SO and 9-Bump WLP Packages
Pin Configurations and Ordering Information appear at end
of data sheet.
Typical Operating Circuit
VCC
(I2C PORT)
µC
RP*
SDA
SCL
PCTLZ
DS2482-100
AD0 IO
AD1
CURRENT-LIMITING
RESISTOR
REFER TO APPLICATION
NOTE 4206
OPTIONAL
CIRCUITRY
1-Wire LINE
1-Wire
DEVICE
1-Wire
DEVICE
1-Wire
DEVICE
*RP = I2C PULLUP RESISTOR (SEE THE APPLICATIONS INFORMATION SECTION FOR RP SIZING).
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
19-4930; Rev 10; 1/15
1 page  
DS2482-100
Single-Channel 1-Wire Master
Pin Description
PIN
SO WLP
1 B3
2 C3
3 C2
4 B1
5 B2
6 A1
7 A2
8 A3
NAME
FUNCTION
VCC
IO
GND
SCL
SDA
PCTLZ
AD1
AD0
Power-Supply Input
Input/Output Driver for 1-Wire Line
Ground Reference
I2C Serial Clock Input. Must be connected to VCC through a pullup resistor.
I2C Serial Data Input/Output. Must be connected to VCC through a pullup resistor.
Active-Low Control Output for an External p-Channel MOSFET. Provides extra power to the 1-Wire
line, e.g., for use with 1-Wire devices that require a higher current temporarily to operate.
I2C Address Inputs. Must be connected to VCC or GND. These inputs determine the I2C slave
address of the device (see Figure 8).
CONFIGURATION
REGISTER
T-TIME OSC
SDA
I2C
INPUT/OUTPUT
CONTROLLER
LINE
XCVR
IO
INTERFACE
SCL CONTROLLER
PCTLZ
AD0
STATUS
REGISTER
AD1
READ DATA
DS2482-100
REGISTER
Figure 1. Block Diagram
Detailed Description
The DS2482-100 is a self-timed 1-Wire master that sup-
ports advanced 1-Wire waveform features including
standard and overdrive speeds, active pullup, and
strong pullup for power delivery. The active pullup
affects rising edges on the 1-Wire side. The strong
pullup function uses the same pullup transistor as the
active pullup, but with a different control algorithm. In
addition, the strong pullup activates the PCTLZ pin,
controlling optional external circuitry to deliver addition-
al power beyond the capabilities of the on-chip pullup
transistor. Once supplied with command and data, the
input/output controller of the DS2482-100 performs
time-critical 1-Wire communication functions such as
reset/presence-detect cycle, read-byte, write-byte, sin-
gle-bit R/W, and triplet for ROM Search, without requir-
ing interaction with the host processor. The host obtains
feedback (completion of a 1-Wire function, presence
pulse, 1-Wire short, search direction taken) through the
Status Register and data through the Read Data
Register. The DS2482-100 communicates with a host
processor through its I2C bus interface in standard
mode or in fast mode. The logic state of two address pins
determines the I2C slave address of the DS2482-100,
allowing up to four devices operating on the same bus
segment without requiring a hub. See Figure 1 for a block
diagram.
www.maximintegrated.com
Maxim Integrated | 5
5 Page 
DS2482-100
Single-Channel 1-Wire Master
1-Wire Single Bit
Command Code
Command Parameter
87h
Bit Byte
Description
Generates a single 1-Wire time slot with a bit value “V” as specified by the bit byte at the 1-Wire
line (see Table 2). A V value of 0b generates a write-zero time slot (Figure 5); a V value of 1b
generates a write-one time slot, which also functions as a read-data time slot (Figure 6). In either
case, the logic level at the 1-Wire line is tested at tMSR and SBR is updated.
Typical Use
Restriction
To perform single-bit writes or reads at the 1-Wire line when single bit communication is
necessary (the exception).
1-Wire activity must have ended before the DS2482-100 can process this command.
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
Command code and bit byte are not acknowledged if 1WB = 1 at the time the command code is
received and the command is ignored.
tSLOT + maximum 262.5ns, counted from the falling SCL edge of the first bit (MSB) of the bit byte.
Begins maximum 262.5ns after the falling SCL edge of the MSB of the bit byte.
Status Register (for busy polling and data reading).
1WB (set to 1 for tSLOT), SBR is updated at tMSR, DIR (may change its state).
1WS, APU, SPU apply.
Table 2. Bit Allocation in the Bit Byte
BIT 7
V
x = Don’t care.
BIT 6
x
BIT 5
x
BIT 4
x
BIT 3
x
BIT 2
x
BIT 1
x
BIT 0
x
VCC
VIH1
VIL1
0V
tF1
RESET PULSE
PRESENCE/SHORT DETECT
PRESENCE PULSE
tSI tMSP
APU CONTROLLED
EDGE
tRSTL
PULLUP
RESISTIVE PULLUP
tRSTH
DS2482-100 PULLDOWN
1-Wire SLAVE PULLDOWN
Figure 4. 1-Wire Reset/Presence-Detect Cycle
www.maximintegrated.com
Maxim Integrated | 11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet DS2482-100.PDF ] | |
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