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PDF LC87F1K64A Data sheet ( Hoja de datos )
| Número de pieza | LC87F1K64A | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Ordering number : ENA2197
LC87F1K64A
CMOS IC
8-bit Microcontroller
with USB-host Controller
64K-byte Flash ROM / 8K-byte RAM / 48-pin
http://onsemi.com
Overview
The LC87F1K64A is an 8-bit microcontroller that, integrates on a single chip a number of hardware features such as
64K-byte flash ROM, 8192-byte RAM, an on-chip debugger, a sophisticated 16-bit timer/counter (may be divided into
8-bit timers), a 16-bit timer (may be divided into 8-bit timers or PWMs), four 8-bit timers with a prescaler, a base timer
serving as a time-of-day clock, two channels of synchronous SIO interface with automatic data transfer capabilities, an
asynchronous/synchronous SIO interface, a single-master I2C/synchronous SIO interface, a UART interface (full
duplex), a full/low-speed USB interface (host control function) × 2 ports, a 12-bit 12-channel AD converter, two
channels of 12-bit PWM, a system clock frequency divider, an infrared remote control receiver circuit, an internal reset
circuit, and a 44-source 10-vector interrupt feature.
Fe■aFtluasrheRsOM
• 65536×8 bits
• Capable of on-board programming with a wide range of
supply voltage from 3.0 to 5.5V
• Block-erasable in 128-byte units
• Data written in 2-byte units
■RAM
• 8192×9 bits
■Package Form
• SQFP48 (7×7): Lead-/halogen-free product
■Bus Cycle Time
• 83.3ns (when CF=12MHz)
Note: The bus cycle time here refers to the ROM read
speed.
■Minimum Instruction Cycle Time (tCYC)
• 250ns (when CF=12MHz)
SQFP48(7X7)
9.0
7.0
36 25
37 24
48 13
1
(0.75)
0.5
12
0.18
0.15
ORDERING INFORMATION
See detailed ordering and shipping information on page 35 of this data sheet.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
July, 2013
ver.1.02
SQFP48(7X7)
71713HKPC 20111124-S00003 No.A2197-1/35
1 page  
LC87F1K64A
■Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillators do not stop automatically.
2) There are three ways of releasing HOLD mode.
(1) Setting the reset pin to a low level.
(2) Generating a reset signal by watchdog timer or low-voltage detection
(3) Occurrence of an interrupt
• HOLD mode: Suspends instruction execution and operation of the peripheral circuits.
1) The PLL, CF, RC and crystal oscillators automatically stop operation.
Note: Low-speed RC oscillator is controlled directly by the watchdog timer and its oscillation in standby mode
is also controlled.
2) There are five ways of releasing HOLD mode.
(1) Setting the reset pin to a low level
(2) Generating a reset signal by the watchdog timer or low-voltage detection
(3) Establishing an interrupt source at one of INT0, INT1, INT2, INT4, and INT5 pins
* INT0 and INT1 HOLD mode release is available only when level detection is configured.
(4) Establishing an interrupt source at port 0
(5) Establishing an bus active interrupt source in the USB host control circuit
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer
and infrared remote control receiver circuit.
1) The PLL, CF and RC oscillators automatically stop operation.
Note: Low-speed RC oscillator is controlled directly by the watchdog timer and its oscillation in standby mode
is also controlled.
Note: The low-speed RC oscillator retains the state that is established on entry into X'tal HOLD mode if the base
timer is running with the low-speed RC oscillator selected as the base timer input clock source.
2) The state of crystal oscillator established when the X'tal HOLD mode is entered is retained.
3) There are seven ways of releasing X'tal HOLD mode.
(1) Setting the reset pin to a low level
(2) Generating a reset signal by the watchdog timer or low-voltage detection
(3) Establishing an interrupt source at one of INT0, INT1, INT2, INT4, and INT5 pins
* INT0 and INT1 X'tal HOLD mode release is available only when level detection is configured.
(4) Establishing an interrupt source at port 0
(5) Establishing an interrupt source in the base timer circuit
(6) Establishing an interrupt source in the infrared remote control receiver circuit
(7) Establishing an bus active interrupt source in the USB host control circuit
■Development Tools
• On-chip debugger: TCB87–Type B + LC87F1K64A or
TCB87–Type C (3-wire communication cable) + LC87F1K64A
■Flash ROM Programming Board
Package
Programming Board
SQFP48 (7×7)
W87F55256SQ
No.A2197-5/35
5 Page 
LC87F1K64A
Continued from preceding page.
Pin Name
I/O
Description
Port 7
P70 to P73
I/O • 4-bit I/O port
• I/O can be specified in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P70: INT0 input / HOLD release input / timer 0L capture input /
watchdog timer output
P71: INT1 input / HOLD release input / timer 0H capture input
P72: INT2 input / HOLD release input / timer 0 event input /
timer 0L capture input / high-speed clock counter input
P73: INT3 input (input with noise filter) / timer 0 event input /
timer 0H capture input / infrared remote control receiver input
AD converter input port: AN8 (P70), AN9 (P71)
Interrupt acknowledge types
Rising
Falling
Rising &
Falling
H Level
INT0
Enable
Enable
Disable
Enable
INT1
Enable
Enable
Disable
Enable
INT2
Enable
Enable
Enable
Disable
INT3
Enable
Enable
Enable
Disable
PWM0
PWM1
UHAD-
UHAD+
UHBD-
UHBD+
RES
XT1
XT2
CF1
CF2
I/O PWM0 and PWM1 output port
General-purpose input port
• Pin functions
PWM0: Audio interface master clock output
PWM1: Audio interface master clock input
I/O USB-A port data I/O pin / general-purpose I/O port
I/O USB-B port data I/O pin / general-purpose I/O port
I/O External reset input / internal reset output
I • 32.768kHz crystal resonator input
• Pin functions
General-purpose input port
AD converter input port: AN10
I/O • 32.768kHz crystal resonator output
• Pin functions
General-purpose I/O port
AD converter input port: AN11
I Ceramic/crystal resonator input
O Ceramic/crystal resonator output
L Level
Enable
Enable
Disable
Disable
Option
No
No
No
No
No
No
No
No
No
No.A2197-11/35
11 Page | ||
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