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PDF LV5230LG Data sheet ( Hoja de datos )
| Número de pieza | LV5230LG | |
| Descripción | 7ch x 17ch LED Driver | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Ordering number : ENA1359A
LV5230LG
Bi-CMOS IC
7ch×17ch LED Driver
Overview
The LV5230LG is a dot-matrix LED driver IC for cell phones.
Features
• 7×17 dot-matrix LED driver
(5×15 dot-matrix supported)
• Each dot can be set for display over the serial bus.
Functions
• LED driver
Column (anode) driving P-channel driver × 17 channels
Row (cathode ) driving N-channel driver × 7 channels
LED current per dot : 25mA maximum
Two flames of 7×17 (5×15) patterns can be set.
7 grayscale level adjustment on a dot basis (PWM duty factor switching)
Reverse display
Horizontal scroll (1 frame/2 frames)
Continuous/single scroll selectable
Vertical scroll (1 frame/2 frames)
Continuous/single scroll selectable
Automatic flashing can be specified per each dot
Interupt output at the end of scroll
Ring tone synchronization function
• LED driving open drain output × 2
http://onsemi.com
Semiconductor Components Industries, LLC, 2013
August, 2013
O0610 SY/10709 MS PC 20081114-S00001 No.A1359-1/27
1 page  
Dot Matrix LED 7 × 17
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
ROW1
ROW2
ROW3
ROW4
ROW5
ROW6
ROW7
2ms
Dot Matrix LED 5 × 15
LV5230LG
Dynamic Display
ROW1
ROW2
ROW3
ROW4
ROW5
ROW1
ROW2
ROW3
ROW4
ROW5
2ms
Dynamic Display
No.A1359-5/27
5 Page 
LV5230LG
Data transfer and acknowledgement response
After establishment of start conditions, data transfer is made by one byte (8 bits).
Data transfer enables continuous transfer of any number of bytes.
Each time the 8-bit data is transferred, the ACK signal is sent from the receive side to the send side.
The ACK signal is issued when SDA on the send side is released and SDA on the receive side is set “L” immediately
after fall of the clock pulse at the SCL eighth bit of data transfer to “L”.
When the next 1-byte transfer is left in the receive state after transmission of the ACK signal from the receive side,
the receive side releases SDA at fall of the SCL ninth clock.
In the I2C bus, there is no CE signal. Instead, 7-bit slave address is assigned to each device and the first byte of
transfer is assigned to the command (R/W) representing the 7-bit slave address and subsequent transfer direction.
The 7-bit address is transferred sequentially from MSB and if the eighth bit is “L”, the second byte is WRITE mode
and if “H”, the second byte is READ mode.
In the READ mode, the ACK signal issued immediately before sending the stop condition must be 1.
In LV5230, the slave address is specified as (1110111).
Write mode
Start
M
S
Slave address
L
S
A
WC
M
S
Register address
L
S
A
C
M
S
B B KB
BKB
Data
LA
SC
BK
Stop
SCL
SDA
1110111
00000010
00010001
Read mode
Start
M
S
Slave address
L
S
A
WC
M
S
B B KB
Data
LAM
SCS
BKB
Data
LA
SC
BK
Stop
SCL
SDA
1110111 1
STATUS
0
STATUS
1
No.A1359-11/27
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet LV5230LG.PDF ] | |
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