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PDF A1454 Data sheet ( Hoja de datos )

Número de pieza A1454
Descripción 3V Hall Effect Linear Sensor
Fabricantes Allegro 
Logotipo Allegro Logotipo



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A1454
3V Hall Effect Linear Sensor with I2C Output
FEATURES AND BENEFITS
• 1 mm thin (TSSOP-08) package
• 2 factory programmed sensitivity options: 2 LSB/G (for
fields up to ±1000 G) and 4 LSB/G (±500 G)
• Temperature-stable sensitivity for NdFeB and ferrite
magnets
• I2C interface for easy integration with support for up to
127 unique addresses
• EEPROM stores factory programmed settings and up to
16 bytes of user information (programmable through the
I2C interface)
• Micro-power sleep mode through I2C command for
minimizing power in battery-operated applications
• Precise recoverability after temperature cycling
• Wide ambient temperature range: –40°C to 125°C
• 12-bit ADC with 10-bit ENOB (Effective Number of
Bits)
Package: 8-Pin TSSOP (suffix LE)
Not to scale
DESCRIPTION
TheA1454 linear Hall effect sensor IC provides a 12-bit digital
output word that is proportional to the strength of the magnetic
field that is present. Its quiescent output value is at mid-scale, and
it comes in 2 different factory programmed sensitivity ranges:
2LSB/G & 4LSB/G. The sensitivity temperature coefficient
is also factory programmed to support either Neodymium or
Ferrite magnets. The A1454 incorporates an I2C interface for
easy integration into a wide variety of applications. The I2C
address can either be set by external resistors or programmed
via EEPROM, to support up to 127 unique I2C addresses,
allowing for multiple ICs on the same bus. It also includes 16
bytes of user programmable EEPROM.
TheA1454 I2C interface provides a user-controlled sleep input
command that puts the device in micro-power mode, which
reduces the current consumption of theA1454. This low power
feature makes theA1454 perfect for portable, battery-operated
applications.
The BiCMOS monolithic process allows the integration of
both high precision analog and high-density digital circuitry.
The A1454 integrates the Hall element, a 12-bit ADC, gain &
offset compensation circuitry, EEPROM memory and the I2C
interface on a single monolithic IC that is packaged in a space
saving surface mount package.
Engineering samples are available on a limited basis. Contact your sales or
applications support office for additional information.
VCC
Sleep
Mode
I2C Serial
SDA
Interface
SCL
Hall
Element
ADC
Digital Controller
EEPROM
Memory
Charge
Pump
Slave
Address
ADC
ADR0
ADR1
GND
Functional Block Diagram
I2C
Master
VCC VCC
VCC
10 kΩ
10 kΩ
VCC
VA1
SCL VCC
VCC
0.1 µF
SDA ADR0
A1454
ADR1
GND
VA0
NC NC
Typical Application Circuit
A1454-DS

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A1454 pdf
A1454
3V Hall Effect Linear Sensor with I2C Output
I2C INTERFACE CHARACTERISTICS*: valid at TA = 25°C, VCC = 3.0 V, and REXT = 10 kΩ; unless otherwise noted
Characteristics
Bus Free Time Between Stop and
Start
Hold Time Start Condition
Setup Time for Repeated Start
Condition
SCL Low Time
SCL High Time
Data Setup Time
Data Hold Time
Setup Time for Stop Condition
Logic Input Low Level (SDA, SCL
pins)
Symbol
tBUF
tndSTA
tsuSTA
tlow
thigh
tsuDAT
thdDAT
tsuSTO
VIL
Test Conditions
Min.
1.3
0.6
0.6
1.3
0.6
100
0
0.6
Typ.
Max.
900
30
Logic Input High Level (SDA, SCL
pins)
VIH
70
Logic Input Current
Output Voltage (SDA pin)
Clock Frequency (SCL pin)
Output Fall Time (SDA pin)
I2C Pull-Up Resistance
Total Capacitive Load for Each of SDA
and SCL Buses
IIN
VOL
fCLK
tf
REXT
CB
VIN = 0 V to VCC
ILOAD = 1.5 mA
RPU = 2.4 kΩ, CB = 100 pF
–1
2.4
*These values are ratiometric to the supply voltage. I2C Interface Characteristics are ensured by design and not factory tested.
*Contact Allegro for 1.8V I2C Bus support.
––
01
– 0.36
– 400
– 250
10 –
– 100
Unit
µs
µs
µs
µs
µs
ns
ns
µs
%VCC
%VCC
µA
V
kHz
ns
pF
t
suSTA
t
hdSTA
t
suDAT
t
hdDAT
t
suSTO
t
BUF
SDA
SCL
t
LOW
t
HIGH
Figure 1: I2C Interface Timing Diagram
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5

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A1454 arduino
A1454
3V Hall Effect Linear Sensor with I2C Output
EEPROM Memory Check
The EEPROM Memory Check provides the capability to vary
the EEPROM reference voltages and compare the data from each
reference voltage, to ensure that no EEPROM memory cells are
corrupted. A high reference voltage is used ensure that 1’s are
correctly programmed and a low reference voltage is used to
ensure that the 0’s are correctly programmed.
The Tables 6 and 7 describe the features available in customer
accessible register EEPROM Check.
Table 6: Customer Accessible Register EEPROM Check
Register Name
EEPROM Check
Register Address
0x1C
25:6
Unused
MM
Bit Number
MS
0
0 MCI
Table 7: Customer Accessible Register EEPROM Check
Parameter Name
Description
Value
MCI: Memory Check Initiate
The MCI bit can be written by the customer to
initiate an EEPROM memory check procedure.
This bit will self-clear upon completion of the
memory test.
0: Reset Condition
1: Start Memory Check
Bit 1
Bit 2
MS[1:0]: Memory Status
MM
Must be set to ‘0’
0
Must be set to ‘0’
0
These are status bits that provide information on
the progress and result of the Memory Check.
These bits are cleared after a read, or a system
reset.
00: Reset Condition
01: Pass - No failure detected.
10: Fail – Failure detected
11: Running - Memory Check ongoing.
In the case of MS [1:0] = [10], i.e. failure
detected, MM will provide additional diagnostic
information, indicating whether the failing
memory reference was the low reference, or the
high reference.
0: Low Reference Failed
1: High Reference Failed
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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