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PDF A25LQ64 Data sheet ( Hoja de datos )
| Número de pieza | A25LQ64 | |
| Descripción | 64M-BIT (x1 / x2 / x4) 3.3V CMOS MXSMIO | |
| Fabricantes | AMIC | |
| Logotipo |  |
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A25LQ64 Series
64M-BIT (x1 / x2 / x4) 3.3V CMOS MXSMIO
(SERIAL MULTI I/O) FLASH MEMORY
Document Title
64M-BIT (x1 / x2 / x4) 3 . 3 V CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
0.5
1.0
1.1
1.2
1.3
1.4
History
Initial issue
Add 16-pin SOP (300mil) package type
Add 8-pin SOP (209mil) package type
Add FAST READ DUAL OUTPUT (3Bh) command
Refine QE bit definition to control only hardware protect function
Change Figure-36-1, 36-2 and refine erase cycling
Final version release
SFDP address 08h ID code 37 changed to 00
SFDP address 38h & 4Ah EB dummy code data bits 04~00 changed
from 00110b to 00100b
Add A25LQ64M-FE type in ordering information
This type fixes QE bit “1”
The hardware protect function is disabled in this type
Add 8-pin DIP package type
Modify the fast program time spec.
Change Figure 7. unique ID to 64 bytes
Issue Date
June 2, 2012
June 28, 2012
July 10, 2012
November 1, 2012
November 19, 2012
January 14, 2013
March 5, 2013
May 9, 2013
July 01, 2013
January 9, 2014
July 3, 2014
Remark
Preliminary
Final
(July, 2014, Version 1.4)
AMIC Technology Corp.
1 page  
Pin Descriptions
Pin Name
Description
S
DI (IO0)
DO (IO1)
C
W (IO2)
IO3
VCC
Chip Select
Serial Data Input (for 1 x I/O) / Serial Data Input & Output
(for 2 x I/O or 4 x I/O read mode)
Serial Data Output (for 1 x I/O) / Serial Data Input & Output
(for 2 x I/O or 4 x I/O read mode)
Serial Clock
Write protection: connect to VSS or Serial Data Input & Output
(for 4 x I/O read mode)
Serial Data Input & Output (for 4 x I/O read mode)
+ 3.3V Power Supply
VSS Ground
NC No Connect
A25LQ64 Series
Block Diagram
Address
Generator
Memory Array
Page Buffer
DI (IO0)
S
W (IO2)
IO3
C
DO (IO1)
(July, 2014, Version 1.4)
Data
Register
SRAM
Buffer
Mode
Logic
State
Machine
Y-Decoder
HV
Generator
Sense
Amplifier
Clock Generator
Output
Buffer
4 AMIC Technology Corp.
5 Page 
A25LQ64 Series
Read Data Bytes at Higher Speed by Dual Output (FAST READ DUAL OUTPUT)
The FAST READ DUAL OUTPUT (3Bh) instruction is similar
to the FAST READ (0Bh) instruction except the data is output
on two pins, IO0 and IO1, instead of just DO. This allows data
to be transferred from the A25LQ64 at twice the rate of
standard SPI devices.
Similar to the FAST READ instruction, the FAST READ
DUAL OUTPUT instruction can operate at the highest
possible frequency of fC (See AC Characteristics). This is
accomplished by adding eight “dummy” clocks after the
24-bit address as shown in figure 4. The dummy clocks allow
the device’s internal circuits additional time for setting up the
initial address. The input data during the dummy clocks is
“don’t care”. However, the IO0 and IO1 pins should be
high-impedance prior to the falling edge of the first data out
clock.
Figure 4. FAST READ DUAL OUTPUT Instruction Sequence and Data-Out Sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
C
Instruction (3Bh)
24-Bit Address
DI 23 22 21 3 2 1 0
MSB
DO High Impedance
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy Byte
DIO switches from input to output
DI 7 6 5 4 3 2 1 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
DO 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
MSB
MSB
MSB
Data Out 1
Data Out 2
Data Out 3
Data Out 4
Note: Address bit A23 is Don’t Care, for A25LQ64
(July, 2014, Version 1.4)
10 AMIC Technology Corp.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet A25LQ64.PDF ] | |
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