PDF UJA1079ATW Data sheet ( Hoja de datos )

Número de pieza	UJA1079ATW
Descripción	LIN core system basis chip
Fabricantes	NXP Semiconductors
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No Preview Available ! UJA1079A LIN core system basis chip Rev. 2 — 31 January 2011 Product data sheet 1. General description The UJA1079A core System Basis Chip (SBC) replaces the basic discrete components commonly found in Electronic Control Units (ECU) with a Local Interconnect Network (LIN) interface. The UJA1079A supports the networking applications used to control power and sensor peripherals by using the LIN interface as a local sub-bus. The core SBC contains the following integrated devices: • LIN transceiver compliant with LIN 2.1, LIN 2.0 and SAE J2602, and compatible with LIN 1.3 • Advanced independent watchdog (UJA1079A/xx/WD versions) • 250 mA voltage regulator for supplying a microcontroller; extendable with external PNP transistor for increased current capability and dissipation distribution • Serial Peripheral Interface (SPI) (full duplex) • 2 local wake-up input ports • Limp home output port In addition to the advantages gained from integrating these common ECU functions in a single package, the core SBC offers an intelligent combination of system-specific functions such as: • Advanced low-power concept • Safe and controlled system start-up behavior • Detailed status reporting on system and sub-system levels The UJA1079A is designed to be used in combination with a microcontroller. The SBC ensures that the microcontroller always starts up in a controlled manner. 1 page NXP Semiconductors 5. Pinning information 5.1 Pinning UJA1079A LIN core system basis chip i.c. 1 i.c. 2 TXDL 3 V1 4 RXDL 5 RSTN 6 INTN 7 EN 8 SDI 9 SDO 10 SCK 11 SCSN 12 i.c. 13 i.c. 14 TEST1 15 WDOFF 16 Fig 2. Pin configuration UJA1079A 32 BAT 31 VEXCTRL 30 TEST2 29 VEXCC 28 WBIAS 27 i.c. 26 DLIN 25 LIN 24 i.c. 23 GND 22 i.c. 21 i.c. 20 i.c. 19 WAKE2 18 WAKE1 17 LIMP 015aaa195 5.2 Pin description Table 2. Symbol i.c. i.c. TXDL V1 RXDL RSTN INTN EN SDI SDO SCK SCSN i.c. i.c. TEST1 WDOFF LIMP Pin description Pin Description 1 internally connected; should be left floating 2 internally connected; should be left floating 3 LIN transmit data input 4 voltage regulator output for the microcontroller (5 V or 3.3 V depending on SBC version) 5 LIN receive data output 6 reset input/output to and from the microcontroller 7 interrupt output to the microcontroller 8 enable output 9 SPI data input 10 SPI data output 11 SPI clock input 12 SPI chip select input 13 internally connected; should be left floating 14 internally connected; should be left floating 15 test pin; pin should be connected to ground 16 WDOFF pin for deactivating the watchdog 17 limp home output UJA1079A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 31 January 2011 © NXP B.V. 2011. All rights reserved. 5 of 46 5 Page NXP Semiconductors UJA1079A LIN core system basis chip SCSN SCK SDI 01 sampled X MSB 02 14 03 13 04 12 15 16 01 LSB X SDO X MSB 14 13 12 floating Fig 4. SPI timing protocol 01 LSB floating 015aaa205 6.2.2 Register map The first three bits (A2, A1 and A0) of the message header define the register address. The fourth bit (RO) defines the selected register as read/write or read only. Table 3. Register map Address bits 15, 14 and 13 000 001 010 011 Write access bit 12 = 0 0 = read/write, 1 = read only 0 = read/write, 1 = read only 0 = read/write, 1 = read only 0 = read/write, 1 = read only Read/Write access bits 11... 0 WD_and_Status register Mode_Control register Int_Control register Int_Status register UJA1079A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 31 January 2011 © NXP B.V. 2011. All rights reserved. 11 of 46 11 Page

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