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PDF NT7606 Data sheet ( Hoja de datos )
| Número de pieza | NT7606 | |
| Descripción | STN LCD Controller / Driver | |
| Fabricantes | NovaTek | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de NT7606 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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NT7606
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Preliminary
1 page  
Pad Configuration
NT7606
5 Ver 1.0
5 Page 
NT7606
Serial Interface (P/S is low)
When the serial interface has been selected (P/S = “L”) then when the chip is in active state (/CS = “L”)
the serial data input (SI) and the serial clock input (SCL) can be received. The serial data is read from
the serial data input pin in the rising edge of the serial clocks D7, D6 through D0, in this order.
At the rising edge fo the 8the serial clock, the serial data (D7 – D0) is converted into 8 bit bus mode
data. The RS input of the DR/IR selection is latched in the rising edge of eighth serial clock (SCL) for
the processing.
Figure 1 is serial interface signal diagram.
/CS
SI (D7)
D7 D6
D5 D4 D3 D2
D1 D0 D7 D6 D5
SCL (D6)
RS
1 2 3 4 5 6 7 8 9 10 11
Figure 1. Diagram of Serial Data Transfer
Chip Select Inputs
The NT7606 has one chip select pads. /CS can interface to a microprocessor when /CS is low . When
this pads are set to high, D0 to D7 are high impedance and RS, /RD (E), /WR (R/W) inputs are
disabled.
Registers
The NT7606 has three 8-bit registers, an Instruction Register (IR), and Data Register (DR) and an
output data register (OR).
During writing operation, the Register Select signal (RS) determines which register will be accessed.
The instruction register stores instruction codes and address information for the Display Data RAM
(DDRAM), Character Generator RAM (CGRAM) and Segment Icon RAM (ICONRAM).
During reading operation, output data register (OR) is used. The output data register temporarily
stores data to be read from the DDRAM, CGRAM and ICONRAM and one of these RAM are selected
by RAM address setting instruction. After RAM address setting, first reading is a dummy cycle in 8-bit
bus mode. The valid data comes from second reading. In 4-bit bus mode, after RAM address setting,
first and second reading is dummy cycles. The valid data comes from third reading. The dummy read
make the address counter (AC) increased by 1.So it is recommended to set address again before
writing, The instruction read cycle is not supported and it is regarded as a no operation cycle.
In 4-bit bus mode, it is needed to transfer 4-bit data (through D7~ D4) by two times .The high order
bits (for 8-bit mode D7~D4) are written before the low order bits (for 8-bit mode D3~D0) in write and
low order bits (for 8-bit mode D3~D0) are read before the high order bits (8-bit mode D3~D0) in read
transaction. The D0~D3 pins are floated in this 4-bits bus mode. After /RES resets, NT7606 considers
first 4-bit data from MPU as high order bits.
11 Ver 1.0
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NT7606.PDF ] | |
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