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PDF XR21B1420 Data sheet ( Hoja de datos )
| Número de pieza | XR21B1420 | |
| Descripción | Enhanced 1-Ch Full-Speed USB UART | |
| Fabricantes | Exar | |
| Logotipo |  |
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XR21B1420
Enhanced 1-Ch Full-Speed USB UART
General Description
The XR21B1420 is an enhanced Universal Asynchronous Receiver and
Transmitter (UART) bridge to USB interface. The USB interface is fully
compliant to the USB 2.0 (Full-Speed) specification with 12 Mbps USB
data transfer rate. The USB interface also supports USB suspend,
resume and remote wakeup operations. The USB Vendor ID, Product ID,
power mode, remote wakeup support, maximum power, and numerous
other settings may be programmed in the on-chip OTP memory via the
USB interface.
The XR21B1420 includes an internal oscillator and does not require an
external crystal/oscillator. Any UART baud rate up to 12 Mbps may be
generated with this internal clock and the fractional baud rate generator.
The UART pins may also be configured as GPIO; direction, state, output
driver type and input pull-up or pull-down resistors are programmed either
through on chip OTP, or on the fly via memory mapped registers.
Large 512-byte TX and RX FIFOs prevent buffer overflow errors and opti-
mize data throughput. Automatic half-duplex direction control and optional
multi drop (9-bit) mode simplify both hardware and software in half-duplex
RS-485 applications.
The XR21B1420 uses the native OS CDC-ACM driver or an Exar supplied
custom driver. Exar provides WHQL/HCK-certified software drivers for
Windows 2000, XP, Vista, 7, 8, 8.1 as well as software drivers for Windows
CE, Linux and Mac OS X. Full source code is available.
The XR21B1420 operates from a single 5V or 3.3V power supply. When
powered with 5V input, a regulated 3.3V output is supplied.
Block Diagram
FEATURES
±15kV ESD on USBD+/USBD-
USB 2.0 Compliant, Full-Speed (12Mbps)
Unique pre-programmed USB serial number
Internally generated 48MHz core clock
Enhanced UART features
Baud rates up to 12 Mbps
Fractional Baud Rate Generator
512-byte TX and 512-byte RX FIFOs
Auto Hardware / Software Flow Control
Multidrop and Half-Duplex Modes
Auto RS-485 Half-Duplex Control
Selectable GPIO or Modem I/O
Up to 10 GPIOs
5V tolerant GPIO inputs
Suspend state GPIO configuration
Configurable clock output
28-pin QFN package
Industrial -40°C to +85°C Temperature Range
APPLICATIONS
Building Automation
Security Systems
Factory and Process Control
ATM Terminals
USB to Serial Controllers
Ordering Information – page 60
USB
Internal
Oscillator
(48MHz)
USB Slave Interface
USB
Descriptors
OTP
Fractional
BRG
512-byte
TX FIFO
512-byte
RX FIFO
Internal
Status and
Control
Registers
GPIOs/
Modem IO
UART
LDO
3V3
TX 1840k
Throughput Comparison
1610k
RX
1380k
Competitor
Exar
1150k
920k
690k
460k
230k
0k
230k
460k
920k
Data Rate (bps)
1840k
© 2014 Exar Corporation
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XR21B1420
Pin No.
Pin Name
16 GPIO8/TXT
17 GPIO7/RS485
18 NC
19 GPIO6/CLK
20 NC
21 NC
22 NC
23 GPIO4/CTS#
24 GPIO5/RTS#/RS485
25 RX
26 TX
27 GPIO2/DSR#
28 GPIO3/DTR#
Type
I/O
I/O
-
I/O
-
-
-
I/O
I/O
I
O
I/O
I/O
Description
General purpose I/O, or UART transmit data indicator. Defaults to GPIO input with internal pull-
up resistor. See “TXT and RXT Pins” on page 15. When configured as transmit indicator, this
pin will toggle at ~10Hz intervals while the UART is transmitting data.
General purpose I/O, or RS-485 half-duplex enable output. Defaults to GPIO input with internal
pull-up resistor.
No Connect.
General purpose I/O, or clock or pulse output. Defaults to GPIO input with internal pull-up
resistor. See “Programmable Output Clock” on page 13.
No Connect.
No Connect.
No Connect.
General purpose I/O, or UART Clear-to-Send input (active low). Defaults to GPIO input with
internal pull-up resistor. See “Automatic RTS/CTS Hardware Flow Control” on page 13.
General purpose I/O, or UART Request-to-Send output (active low), or auto RS-485 half-
duplex control. Defaults to GPIO input with internal pull-up resistor. See “Automatic RTS/CTS
Hardware Flow Control” on page 13 or “Multidrop mode with address matching” on page 14.
UART Receive Data.
UART Transmit Data.
General purpose I/O, or UART Data-Set-Ready input (active low). Defaults to GPIO input with
internal pull-up resistor. See “Automatic DTR/DSR Hardware Flow Control” on page 14.
General purpose I/O, or UART Data-Terminal-Ready push-pull output (active low). Defaults to
GPIO input with internal pull-up resistor. See “Automatic DTR/DSR Hardware Flow Control” on
page 14.
Type: I = Input, O = Output, I/O = Input/Output, PWR = Power, OD = Open-Drain
© 2014 Exar Corporation
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XR21B1420
parity is selected, the TX FIFO contains 8 bits data and the parity bit is automatically generated and transmitted. If 9 bit data
is selected, parity cannot be generated. The 9th bit will not be transmitted unless the wide mode is enabled.
Wide Mode Transmit
When both 9 bit data and wide mode are enabled, two bytes of data will be written into the TX FIFO. The first byte is the first
8 bits (data bits 7-0) of the 9-bit data. Bit-0 of the second byte is bit-8 of the 9-bit data. The data that is transmitted on the TX
pin is as follows: start bit, 9-bit data, stop bit. Wide mode may be enabled using the TX_WIDE_MODE and RX_WIDE_-
MODE registers.
Receiver
The receiver consists of a 512-byte RX FIFO and a Receive Shift Register (RSR). Data that is received in the RSR via the
RX pin is transferred into the RX FIFO. Data from the RX FIFO is sent to the USB host by in response to a bulk-in request.
Depending on the mode, error / status information for that data character may or may not be stored in the RX FIFO with the
data.
Normal receive operation with 5, 6, 7 or 8-bit data
Received data is stored in the RX FIFO. Any parity, framing or overrun error or break status information related to the data
is discarded. The receive data format is shown in Figure 4.
7, 8, or 9 bit data
1ST byte 7 6 5 4 3 2 1 0 7 = ‘0’ in 7 bit mode
Figure 4: Receive Data Format
Normal receive operation with 9-bit data
The first 8 bits of data received is stored in the RX FIFO. The 9th bit as well as any parity, framing or overrun error or break
status information related to the data is discarded.
Wide mode receive operation with 5, 6, 7 or 8-bit data
Two bytes of data are loaded into the RX FIFO for each byte of data received. The first byte is the received data. The sec-
ond byte consists of the error bits and break status. Wide mode receive data format is shown in Figure 5.
© 2014 Exar Corporation
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XR21B1420.PDF ] | |
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