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Numéro de référence | CH7002D | ||
Description | Scalable VGA to NTSC/PAL Encoder | ||
Fabricant | ETC | ||
Logo | |||
1 Page
CHRONTEL
CH7002D
Preliminary
Scalable VGA to NTSC/PAL Encoder
Features
• Fully integrated solution for PC to TV display
• TrueScale TM rendering engine supports underscan
operation for both 640x480 or 800x600 inputs †
• Advanced 3-line digital flicker filtering with
programmable algorithm selections †
• Fully programmable through I2C port or hardware
(pin-based) controls
• Wide range of VGA software drivers for full
synchronization and image positioning
• Auto-detection of TV presence
• Programmable power management features three
power-down modes
• Supports both NTSC and PAL (B, D, G, H, or I) TV
formats onto both composite and S-Video
• Triple 8-bit ADC inputs and triple 8-bit DAC outputs
• On-chip reference generation and loop filter
• Offered in 44-pin PLCC package
General Description
Chrontel’s CH7002 VGA to NTSC/PAL encoder is a stand-
alone integrated circuit which provides a PC 99 compliant
solution for TV output. It accepts RGB analog inputs directly
from VGA controllers and converts them directly into NTSC
or PAL TV format, with simultaneous composite and
S-Video outputs.
This circuit integrates a digital NTSC/PAL encoder with 8-
bit ADC and DAC interfaces, a 3-line vertical filter, and low-
jitter phase-locked loop to create outstanding quality video.
Through Chrontel’s TrueScale TM rendering technology, the
CH7002 supports full vertical and horizontal underscan
operation from either 640x480 or 800x600 input to either
NTSC or PAL outputs.
A high level of performance along with full programmability
makes the CH7002 ideal for system-level PC or Web
browser solutions. All features are software programmable,
through a standard I2C port, to enable fully integrated system
solutions by using a TV as the primary display device.
† Patent number 5,781,241
PMODE
SD SC ADDR
I2C REGISTER & CONTROL
BLOCK
LINE
MEMORY
RSET
RSET
RR
ADC
Y
LINE RENDERING ENGINE
G
G COLOR
U
ADC
SPACE
-SCALING
CONVERTER
-DEFLICKERING
BB
V -SCAN CONVERSION
ADC
SYSTEM CLOCK
Y
U DIGITAL
NTSC/PAL
ENCODER
V & FILTER
DAC
DAC
DAC
VREF
PLL
TIMING & SYNC GENERATOR
OSC
VREF1 VREF2
XCLK
HV
Figure 1: Functional Block Diagram
XI XO
Y
CVBS
C
CLKOUT
201-0000-029 Rev 6.1, 8/2/99
1
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Pages | Pages 36 | ||
Télécharger | [ CH7002D ] |
No | Description détaillée | Fabricant |
CH7002D | Scalable VGA to NTSC/PAL Encoder | ETC |
CH7002D-V | Scalable VGA to NTSC/PAL Encoder | ETC |
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