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PDF CGS74B2525 Data sheet ( Hoja de datos )

Número de pieza CGS74B2525
Descripción 1-to-8 Minimum Skew Clock Driver
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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September 1995
CGS74B2525
1-to-8 Minimum Skew Clock Driver
General Description
This minimum skew clock driver is designed for Clock Gen-
eration and Support (CGS) applications operating well
above 20 MHz (33 MHz 50 MHz) The device guarantees
minimum output skew across the outputs of a given device
and also from device-to-device Skew parameters are also
provided as a means to measure duty cycle requirements as
those found in high speed clocking systems The ’B2525 is
a minimum skew clock driver with one input driving eight
outputs specifically designed for signal generation and clock
distribution applications
Features
Y Clock Generation and Support (CGS) Device Ideal for
high frequency signal generation or clock distribution
applications
Y CGS74B version features National’s Advanced Bipolar
FAST LSI process
Y 1-to-8 low skew clock distribution
Y 600 ps pin-to-pin output skew
Y Specifications for device-to-device variation of propaga-
tion delay
Y Specification for transition skew to meet duty cycle
requirements
Y Center pin VCC and GND configuration to minimize high
speed switching noise
Y Current sourcing 48 mA and current sinking of 64 mA
Y Low dynamic power consumption above 20 MHz
Y Guaranteed 4 kV ESD protection
Logic Symbol
Connection Diagram
Pin Assignment
for DIP and SOIC
TL F 10907 – 1
TL F 10907 – 2
FAST and TRI-STATE are registered trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 10907
RRD-B30M115 Printed in U S A

1 page




CGS74B2525 pdf
Timing Diagrams
TL F 10907 – 16
Test Circuit
TL F 10907 – 17
RL is 500X
CL is 50 pF for all prop delays and skew measurements
TL F 10907 – 18
5

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