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National Semiconductor - Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI

Numéro de référence CGS702V
Description Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI
Fabricant National Semiconductor 
Logo National Semiconductor 





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CGS702V fiche technique
September 1995
CGS702V
Commercial Low Skew PLL 1 to 9 CMOS Clock Driver
with Improved EMI
General Description
The CGS702 is an off-the-shelf clock driver specifically de-
signed for today’s high speed processors It provides low
skew outputs which are produced at different frequencies
from three fixed input references The CGS702 is a reduced
EMI version of the CGS700 The XTALIN input pin is de-
signed to be driven from three distinct crystal oscillators run-
ning at 25 MHz 33 MHz or 40 MHz
The PLL using a charge pump and an internal loop filter
multiplies this input frequency to create a maximum output
frequency of four times the input
The device includes a TRI-STATE control pin to disable
the outputs while the PLL is still in lock This function allows
testing the board without having to wait to acquire the lock
once the testing is complete
(Continued)
Features
Y Reduced EMI compared to CGS700 (refer to EMI
characteristics)
Y Guaranteed and tested 500 ps pin-to-pin skew (TOSHL
and TOSLH) on 1x outputs
Y PentiumTM and PowerPCTM compatible
Y Output buffer of nine drivers for large fanout
Y 25 MHz – 160 MHz output frequency range
Y Outputs operating at 4x 2x 1x of the reference
frequency for multi-frequency bus applications
Y Selectable output frequency
Y Internal loop filter to reduce noise and jitter
Y Separate Analog and digital VCC and Ground pins
Y Low frequency test mode by disabling the PLL
Y Implemented on National’s Core CMOS process
Y Symmetric output current drive
a30 mA b30 mA IOL IOH
Y 28-pin PCC for optimum skew performance
Y Guaranteed 2 kV ESD protection
Connection Diagram
Pin Assignment for PLCC
TL F 12386 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
PentiumTM is a trademark of Intel Corporation
PowerPCTM is a trademark of International Business Machines Corporation
Pin Description
PLCC Package
Pin Name
Description
1 VCC
2 SKWSEL
Digital VCC
Skew Test Selector Pin
3 CLK4
4x Clock Output
4 VCC
5 XTALIN
Digital VCC
Crystal Oscillator Input
6 GND
Digital Ground
7 CLK1 0
1x Clock Output
8 VCC
9 CLK1 1
Digital VCC
1x Clock Output
10 GND
Digital Ground
11 CLK1 2
1x Clock Output
12 TRI-STATE Output TRI-STATE Control
13 SKWTST
Skew Testing Pin
14 CLK1 3
1x Clock Output
15 GND
Digital Ground
16 CLK1 4
1x Clock Output
17 VCC
18 EXTCLK
Digital VCC
External Test Clock
19 GNDA
Analog Ground
20 VCCA
21 EXTSEL
Analog VCC
External Clock MUX Selector
22 GND
Digital Ground
23 CLK1 5
1x Clock Output
24 VCC
25 CLK1 6
Digital VCC
1x Clock Output
26 CLK1SEL
CLK1 Multiplier Selector
27 GND
Digital Ground
28 CLK2
2x Clock Output
C1995 National Semiconductor Corporation TL F 12386
RRD-B30M105 Printed in U S A

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