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PDF SAA7715AH Data sheet ( Hoja de datos )
| Número de pieza | SAA7715AH | |
| Descripción | Digital Signal Processor | |
| Fabricantes | Philips | |
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INTEGRATED CIRCUITS
DATA SHEET
SAA7715AH
Digital Signal Processor
Preliminary specification
2003 Mar 13
1 page  
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handbook, full pagewidth
IIS_BCK1
IIS_WS1
IIS_IN1
IIS_IN4
1
2
3
5
24 25
SAA7715AH
6
IIS_IN2
478
35 17 23 16
XRAM YRAM
DSP CORE
37 15 21 14 10
31
IIS_OUT1
30
IIS_OUT2
29
IIS_OUT3
28
IIS_OUT4
33
IIS_BCK
32
IIS_WS
IIS_IN3 9
÷2
S
PLL
DSP CLOCK
PRAM PROM
STEREO
DAC
n × fs
CLOCK
34
VOUTL
36
VOUTR
39
POM
38
VREFDA
22 41
TCB
I2C-BUS
44 43 42 40 20 19 26
13 12 11
WS_PLL
27 18 MHC320
Fig.1 Block diagram.
5 Page 
Philips Semiconductors
Digital Signal Processor
Preliminary specification
SAA7715AH
8.5 Digital serial inputs/outputs and SPDIF inputs
8.5.1 DIGITAL SERIAL INPUTS/OUTPUTS
For communication with external digital sources a digital
serial bus is implemented. It is a serial 3-line bus, having
one line for data, one line for clock and one line for the
word select. For external digital sources the SAA7715AH
acts as a slave, so the external source is master and
supplies the clock.
For the I2S-bus format itself see the official specification
from Philips.
The digital serial input is capable of handling Philips
I2S-bus and LSB-justified formats of 16, 18, 20 and 24 bits
word sizes. The sampling frequency can be 32 up to
96 kHz. See “9.8 I2C-bus memory map definition” for the
bits that must be programmed, for selection of the desired
serial format.
See Fig.3 for the general waveforms of the possible
formats.
When the applied word length exceeds 24 bits, the LSBs
are skipped.
The digital serial input/output circuitry is limited in handling
the number of BCK pulses per WS period. The maximum
allowed number of bit clocks per WS period is 256. Also
the number of bit clocks during WS LOW and HIGH must
be equal (50% WS duty factor) only for the LSB-justified
formats.
There are two modes in which the digital inputs can be
used (the mode is selectable via an I2C-bus bit):
• Use up to 4 digital serial inputs (8ch) with common WS
and BCK signal (8ch IN and 8ch OUT + 2ch FSDAC
output)
• Use one of the 2 SPDIF inputs as source instead of the
use of the digital serial inputs (2ch IN and
8ch OUT + One 2ch FSDAC output).
8.5.2 SPDIF INPUTS
Two separate SPDIF receivers are available, one shared
with digital serial input 2 (SPDIF1) and one with the digital
serial input 3 (SPDIF2). The sample frequency at which
the SPDIF inputs can be used must be in the range of
32 to 96 kHz.
There are few control signals available from the SPDIF
input stage. These are connected to flags of the DSP:
• A lock signal indicating if the SPDIF input 1 or 2 is in
lock
• The pcm_audio/non-pcm_audio bit indicating if an audio
or data stream is detected on SPDIF input 1 or 2. The
FSDAC output will NOT be muted in the event of
non-audio PCM stream. This status bit can be read via
the I2C-bus, the microprocessor controller can decide to
put the DAC into MUTE (via pin POM).
Handling of channel status bits: The first 40 (of 192)
channel status bits of the selected SPDIF source (0FFBH,
bit 20), will come available in the I2C-bus registers
0FF2H to 0FF5H. Two registers 0FF2H to 0FF3H contain
the information for the right channel, the other two
(0FF4H to 0FF5H) contain the information for the left
channel. The information can be read via I2C-bus or by the
DSP program.
The design fulfils the digital audio interface specification
“IEC 60958-1 Ed2, part 1, general part IEC 60958-3 Ed2,
part 3, consumer applications”.
2003 Mar 13
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SAA7715AH.PDF ] | |
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