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Intersil Corporation - CMOS 6-Bit Latch and Decoder Memory Interfaces

Numéro de référence CDP1882
Description CMOS 6-Bit Latch and Decoder Memory Interfaces
Fabricant Intersil Corporation 
Logo Intersil Corporation 





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CDP1882 fiche technique
March 1997
CDP1881C,
CDP1882, CDP1882C
CMOS 6-Bit Latch
and Decoder Memory Interfaces
Features
• Performs Memory Address Latch and Decoder
Functions Multiplexed or Non-Multiplexed
• Decodes Up to 16K Bytes of Memory
• Interfaces Directly with CDP1800-Series Microproces-
sors at Maximum Clock Frequency
• Can Replace CDP1866 and CDP1867 (Upward Speed
and Function Capability)
Ordering Information
PACKAGE
5V
10V
PDIP
CDP1881CE
-
PDIP
CDP1882CE
-
PDIP
CDP1882CEX
Burn-In
-
SBDIP
- CDP1882D
TEMP.
RANGE
(oC)
PKG.
NO.
-40 to +85 E20.3
-40 to +85 E18.3
-40 to +85 E18.3
-40 to +85 D18.3
Description
The CDP1881C, CDP1882 and CDP1882C are CMOS 6-bit
memory latch and decoder circuits intended for use in
CDP1800 series microprocessor systems. They can inter-
face directly with the multiplexed address bus of this system
at maximum clock frequency, and up to four 4K x 8-bit mem-
ories to provide a 16K byte memory system. With four 2K x
8-bit memories an 8K byte system can be decoded.
The devices are also compatible with non-multiplexed
address bus microprocessors. By connecting the clock input
to VDD, the latches are in the data-following mode and the
decoded outputs can be used in general purpose memory-
system applications.
The CDP1881C, CDP1882 and CDP1882C are intended for
use with 2K or 4K byte RAMs and are identical except that in
the CDP1882 MWR and MRD are excluded.
The CDP1882 is functionally identical to the CDP1882C. It
differs in that the CDP1882 has recommended operating
voltage range of 4V to 10.5V and the C version has a recom-
mended operating voltage range of 4V to 6.5V.
The CDP1881C, CDP1882 and CDP1882C are supplied in
20 lead and 18 lead packages, respectively. The
CDP1881C is supplied only in a dual-in-line plastic pack-
age (E suffix). The CDP1882 is supplied in dual-in-line,
hermetic side-brazed ceramic (D suffix) and in plastic (E
suffix) packages.
Pinouts
CDP1881C
(PDIP)
TOP VIEW
CDP1882, CDP1882C
(PDIP, CERDIP)
TOP VIEW
CLOCK 1
MA5 2
MA4 3
MA3 4
MA2 5
MA1 6
MA0 7
MRD 8
MWR 9
VSS 10
20 VDD
19 A8
18 A9
17 A10
16 A11
15 CS0
14 CS1
13 CS2
12 CS3
11 CE
CLOCK 1
MA5 2
MA4 3
MA3 4
MA2 5
MA1 6
MA0 7
CE 8
VSS 9
18 VDD
17 A8
16 A9
15 A10
14 A11
13 CS0
12 CS1
11 CS2
10 CS3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-1
File Number 1367.2

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