PDF CDP1855 Data sheet ( Hoja de datos )

Número de pieza	CDP1855
Descripción	8-Bit Programmable Multiply/Divide Unit
Fabricantes	Intersil Corporation
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No Preview Available ! March 1997 CDP1855, CDP1855C 8-Bit Programmable Multiply/Divide Unit Features • Cascadable Up to 4 Units for 32-Bit by 32-Bit Multiply ÷or 64 32-Bit Divide ÷• 8-Bit by 8-Bit Multiply or 16 8-Bit Divide in 5.6µs at 5V or 2.8µs at 10V • Direct Interface to CDP1800-Series Microprocessors • Easy Interface to Other 8-Bit Microprocessors • Signiﬁcantly Increases Throughput of Microprocessor Used for Arithmetic Calculations Ordering Information PACKAGE TEMP. RANGE 5V PDIP -40oC to +85oC CDP1855CE PKG. 10V NO. CDP1855E E28.6 Burn-In SBDIP CDP1855CEX - E28.6 -40oC to +85oC CDP1855CD CDP1855D D28.6 Burn-In CDP1855CDX - D28.6 Description The CDP1855 and CDP1855C are CMOS 8-bit multi- ply/divide units which can be used to greatly increase the capabilities of 8-bit microprocessors. They perform multiply and divide operations on unsigned, binary operators. In general, microprocessors do not contain multiply or divide instructions and even efﬁciently coded multiply or divide subroutines require considerable memory and execution time. These multiply/divide units directly interface to the CDP1800-series microprocessors via the N-lines and can easily be conﬁgured to ﬁt in either the memory or I/O space of other 8-bit microprocessors. The multiple/divide unit is based on a method of multiplying by add and shift right operations and dividing by subtract and shift left operations. The device is structured to permit cas- cading identical units to handle operands up to 32 bits. The CDP1855 and CDP1855C are functionally identical. They differ in that the CDP1855 has a recommended operating voltage range of 4V to 10.5V, and the CDP1855C, a recommended operating voltage range of 4V to 6.5V. The CDP1855 and CDP1855C types are supplied in a 28 lead hermetic dual-in-line ceramic package (D sufﬁx) and in a 28 lead dual-in-line plastic package (E sufﬁx). The CDP1855C is also available in chip form (H sufﬁx). Pinout 28 LEAD DIP TOP VIEW Circuit Conﬁguration +V CE 1 CLEAR 2 CTL 3 C.O./O.F. 4 YL 5 ZL 6 SHIFT 7 CLK 8 STB 9 RD/WE 10 RA2 11 RA1 12 RA0 13 VSS 14 28 VDD 27 CN0 26 CN1 25 CI 24 YR 23 ZR 22 BUS 7 21 BUS 6 20 BUS 5 19 BUS 4 18 BUS 3 17 BUS 2 16 BUS 1 15 BUS 0 CLEAR XTAL N0 N1 N2 TPB MRD CDP1802 EF BUS CLEAR CLK CE RA0 C1 RA1 CN0 RA2 CN1 STB RD/WE CDP1855 YL ZR CTL C0 YR ZL BUS FIGURE 1. MDU ADDRESSED AS I/O DEVICE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 \| Copyright © Intersil Corporation 1999 4-47 File Number 1053.2 1 page CDP1855, CDP1855C A second division is performed using the remainder from the ﬁrst division (in Y) as the more signiﬁcant 8N-bits of the divi- dend and the less signiﬁcant half of the original dividend loaded into the Z register. The divisor in X remains unaltered and is, by deﬁnition, larger than the remainder from the ﬁrst division which is in Y. The resulting value in Z becomes the less signiﬁcant 8N-bits of the ﬁnal quotient and the value in Y is, as usual, the remainder. Extending this technique to more steps allows division of any size number by an 8N-bit divisor. Note that division by zero is never permitted and must be tested for and handled in software. The following example illustrates the use of this algorithm. Example: Assume three MDU's capable of a by 24-bit division. The problem is to divide 00F273, 491C06H by 0003B4H. Step 1: 000000 , 00F273 / 0003B4 = 000041 R=0001BF Y Z(MS) X Z1 Y1 Step 2: 0001BF , 491C06 / 0003B4 = 78C936 R=00000E Y1 Z(LS) X Z2 Y2 Result: 000041 , 78C936 R=00000E Z1 Z2 Y2 The Z register can simply be reset using bit 2 of the control word and another divide can be done in order to further divide the remainder. 3. Multiply Operation For a multiply operation the two numbers to be multiplied are loaded in the X and Z registers. The result is in the Y and Z register with Y being the more signiﬁcant half and Z the less signiﬁcant half. The X register will be unchanged after the operation is completed. The original contents of the Y register are added to the product of X and Z. Bit 3 of the control word will reset register Y to 0 if desired. Functional Description of CDP1855 Terminals CE - Chip Enable (Input): A high on this pin enables the CDP1855 MDU to respond to the select lines. All cascaded MDU's must be enabled together. CE also controls the three-state C.O./O.F., output of the most signiﬁcant MDU. Clear (Input): The CDP1855 MDU(s) must be cleared upon power-on with a low-on this pin. The clear signal resets the sequence counters, the shift pulse generator, and bits 0 and 1 of the control register. CTL - Control (Input): This is an input pin. All CTL pins must be wired together and to the YL of the most signiﬁcant CDP1855 MDU and to the ZR of the least signiﬁcant CDP1855 MDU. This signal is used to indicate whether the registers are to be operated on or only shifted. C.O./O.F. - Carry Out/Over Flow (Output): This is a three-state output pin. It is the CDP1855 Carry Out signal and is connected to Cl (CARRY-IN) of the next more signiﬁcant CDP1855 MDU, except for on the most signiﬁcant MDU. On that MDU it is an overﬂow indicator and is enabled when chip enables is true. A low on this pin indicates that an overﬂow has occurred. The overﬂow signal is latched each time the control register is loaded, but is only meaningful after a divide command. YL, YR - Y-Left, Y-Right: These are three-state bi-directional pins for data transfer between the Y registers of cascaded CDP1855 MDU's. The YR pin is an output and YL is an input during a multiply and the reverse is true at all other times. The YL pin must be connected to the YR pin of the next more signiﬁcant MDU. An exception is that the YL pin of the most signiﬁcant CDP1855 MDU must be connected to the ZR pin of the least signiﬁcant MDU and to the CTL pins of all MDU's. Also the YR pin of the least signiﬁcant MDU is tied to the ZL pin of the most signiﬁcant MDU. ZL, ZR - Z-Left, Z-Right: These are three-state bi-directional pins for data transfers between the “Z” registers of cascaded MDU's. The ZR pin is an output and ZL is an input during a multiply and the reverse is true at all other times. The ZL pin must be tied to the YR pin of the next more signiﬁcant MDU. An exception is that the ZL in of the most signiﬁcant MDU must be con- nected to the YR pin of the least signiﬁcant MDU. Also, the ZR pin of the least signiﬁcant MDU is tied to the YL of the most signiﬁcant MDU. Shift - Shift Clock: This is a three-state bi-directional pin. It is an output on the most signiﬁcant MDU. And an input on all other MDU's. It provides the MDU system timing pulses. All SHIFT pins must be connected together for cascaded operation. A maximum of the 8N +1 shifts are required for an operation where "N" equals the number of MDU devices that are cascaded. CLK - Clock (Input): This pin should be grounded on all but the most signiﬁcant MDU. There is an optional reduction of clock frequency avail- able on this pin if so desired, controlled by bit 7 of the control byte. STB - Strobe (Input): When RD/WE is low, data is latched from bus lines on the falling edge of this signal. It may be asynchronous to the clock. Strobe also increments the selected register's sequence counter during reads and writes. TPB would be used in CDP1800 systems. 4-51 5 Page Y-----3---Y---X-2----3Y---X-1---2Z----X3----Z1----2---Z----1- = Z3Z2Z1 + X-Y----33---YX----22----YX----11- CDP1855, CDP1855C DATA BUS 8 CLOCK 8 VDD BUS RD/ STB CLR WE CN1 CN0 RA0 CLK RA1 SHIFT RA2 YL CDP1855 YR ZL ZR O.F. C.I. CE CTL 8 VDD BUS RD/ STB CLR WE CN1 CN0 RA0 CLK RA1 SHIFT RA2 YL CDP1855 YR ZL ZR C.O. C.I. CE CTL 8 VDD BUS RD/ STB CLR WE CN1 CN0 RA0 CLK RA1 SHIFT RA2 YL CDP1855 YR ZL ZR C.O. C.I. CE CTL VDD EF1 BUS MRD TPB CLEAR N2 N1 N0 TO CPU MOST SIGNIFICANT LEAST SIGNIFICANT VDD OR I/O SELECT FIGURE 5. CASCADING THREE MDU’s (CDP1855) IN AN 1800 SYSTEM WITH MDU’s BEING ACCESSED AS I/O PORTS IN PROGRAMMING EXAMPLE DATA BUS VDD BUS RD/ STB CLR WE CN1 CN0 RA0 CLK RA1 SHIFT RA2 YL CDP1855 YR ZL ZR O.F. C.I. CE CTL VDD BUS RD/ STB CLR WE CN1 CN0 RA0 CLK RA1 SHIFT RA2 YL CDP1855 YR ZL ZR C.O. C.I. CE CTL VDD BUS RD/ STB CLR WE CN1 CN0 RA0 CLK RA1 SHIFT RA2 YL CDP1855 YR ZL ZR C.O. C.I. CE CTL CLOCK EF1 BUS MRD TPB CLEAR N2 N1 N0 BUS RD/ STB CLR WE CN1 CN0 RA0 CLK RA1 SHIFT RA2 YL CDP1855 YR ZL ZR C.O. C.I. CE CTL VDD MOST SIGNIFICANT FIGURE 6. CASCADING FOUR MDU’s (CDP1855) LEAST SIGNIFICANT 4-57 11 Page

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