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CDP1822C fiches techniques PDF

Intersil Corporation - High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM

Numéro de référence CDP1822C
Description High-Reliability CMOS 256-Word x 4-Bit LSI Static RAM
Fabricant Intersil Corporation 
Logo Intersil Corporation 





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CDP1822C fiche technique
CDP1822C/3
March 1997
High-Reliability CMOS
256-Word x 4-Bit LSI Static RAM
Features
Description
• For Applications in Aerospace, Military, and Critical
Industrial Equipment
• Interfaces Directly with CDP1802 Microprocessor
• Very Low Operating Current
- At VDD = 5V and Cycle Time = 1µs . . . . . . 4mA (Typ)
• Static CMOS Silicon-On-Sapphire Circuitry
- CD4000 Series Compatible
• Industry Standard Pinout
• Two Chip Select Inputs - Simple Memory Expansion
• Memory Retention for Standby. . . . . . . . . . . . . 2V (Min)
Battery Voltage
• Single Power Supply Operation . . . . . . . . . . 4V to 6.5V
• High Noise Immunity 30% of VDD. . . . . . . . . 4V to 6.5V
• Output Disable for Common I/O Systems
• Three-State Data Output for Bus Oriented Systems
The CDP1822C/3 is a 256 word by 4-bit random access
memory designed for use in memory systems where high
speed, low operating current, and simplicity in use are
desirable. The CDP1822 features high speed and excellent
noise immunity. It has separate data inputs and outputs and
utilizes a single power supply of 4V to 6.5V.
Two Chip Select inputs simplify system expansion. An output
Disable control provides Wire-OR-capability and is also
useful in common Input/Output systems. The Output Disable
input allows this RAM to be used in common data Input/Out-
put systems by forcing the output into a high impedance
state during a write operation independent of the Chip Select
input condition. The output assumes a high impedance state
when the Output Disable is at high level or when the chip is
deselected by CS1 and/or CS2.
The high noise immunity of the CMOS technology is
preserved in this design. For TTL interfacing at 5V operation,
excellent system noise margin is preserved by using an
external pull-up resistor at each input.
• Separate Data Inputs and Outputs
• Latch-Up-Free Transient Radiation Tolerance
Ordering Information
PACKAGE
SBDIP
TEMP. RANGE
-55oC to +125oC
PART
NUMBER
CDP1822CD3
PKG. NO.
D22.4A
Pinout
CDP1822C/3 (SBDIP)
TOP VIEW
A3 1
A2 2
A1 3
A0 4
A5 5
A6 6
A7 7
VSS 8
DI1 9
DO1 10
DI2 11
22 VDD
21 A4
20 R/W
19 CS1
18 O. D.
17 CS2
16 DO4
15 DI4
14 DO3
13 DI3
12 DO2
OPERATIONAL MODES
INPUTS
MODE
CHIP
SELECT
1
(CS1)
CHIP
SELECT
2
(CS2)
OUTPUT
DISABLE
(OD)
READ/
WRITE
(R/W)
OUTPUT
Read
0
1
0 1 Read
Write
0
1
0 0 Data In
Write
0
1
1 0 High
Impedance
Standby
1
X
X X High
Impedance
Standby
X
0
X X High
Impedance
Output
Disable
X
X
1 X High
Impedance
Logic 1 = High, Logic 0 = Low, X = Don’t Care
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-19
File Number 2981.1

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