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PDF ADSP-BF518 Data sheet ( Hoja de datos )
| Número de pieza | ADSP-BF518 | |
| Descripción | Blackfin Embedded Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Blackfin
Embedded Processor
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
FEATURES
Up to 400 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Wide range of operating voltages. See Operating Conditions
on Page 22
Qualified for Automotive Applications. See Automotive
Products on Page 67
168-ball CSP_BGA or 176-lead LQFP_EP (with exposed pad)
MEMORY
116K bytes of on-chip memory
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Optional 16M bit SPI flash with boot option
Flexible booting options from internal SPI flash, OTP
memory, external SPI/parallel memories, or from SPI/UART
host devices
Code security with Lockbox secure technology
One-time-programmable (OTP) memory
Memory management unit providing memory protection
PERIPHERALS
IEEE 802.3-compliant 10/100 Ethernet MAC with IEEE 1588
support (ADSP-BF518/ADSP-BF518F16 only)
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
2 dual-channel, full-duplex synchronous serial ports
(SPORTs), supporting 8 stereo I2S channels
12 peripheral DMAs, 2 mastered by the Ethernet MAC
2 memory-to-memory DMAs with external request lines
Event handler with 56 interrupt inputs
2 serial peripheral interfaces (SPI)
Removable storage interface (RSI) controller for MMC, SD,
SDIO, and CE-ATA
2 UARTs with IrDA support
2-wire interface (TWI) controller
Eight 32-bit timers/counters with PWM support
3-phase 16-bit center-based PWM unit
32-bit general-purpose counter
Real-time clock (RTC) and watchdog timer
32-bit core timer
40 general-purpose I/Os (GPIOs)
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
RTC
OTP
WATCHDOG TIMER
PERIPHERAL
ACCESS BUS
JTAG TEST AND EMULATION
B
INTERRUPT
CONTROLLER
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
DMA
CONTROLLER
16 DMA CORE BUS
EXTERNAL ACCESS BUS
DMA
EXTERNAL
BUS
EXTERNAL PORT
FLASH, SDRAM CONTROL
BOOT
ROM
COUNTER
3-PHASE PWM
TIMER7–0
TWI
SPORT1-0
RSI (SDIO)
PPI
UART1–0
EMAC
SPI1
SPI0
16M bit SPI Flash
(See Table 1)
Figure 1. Functional Block Diagram
PORTS
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
instruction can be issued in parallel with two 16-bit instruc-
tions, allowing the programmer to use many of the core
resources in a single instruction cycle.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
The ADSP-BF51x processors view memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory, external memory, and I/O control
registers, occupy separate sections of this common address
space. The memory portions of this address space are arranged
in a hierarchical structure to provide a good cost/performance
balance of some very fast, low-latency on-chip memory as cache
or SRAM, and larger, lower-cost and performance off-chip
memory systems. The memory map for both internal and exter-
nal memory space is shown in Figure 3.
0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA1 4000
0xFFA1 0000
0xFFA0 8000
0xFFA0 4000
0xFFA0 0000
0xFF90 8000
0xFF90 4000
0xFF90 0000
0xFF80 8000
0xFF80 4000
0xFF80 0000
0xEF00 8000
0xEF00 0000
0x2040 0000
0x2030 0000
0x2020 0000
0x2010 0000
0x2000 0000
0x08 00 0000
0x0000 0000
CORE MMR REGISTERS (2M BYTES)
SYSTEM MMR REGISTERS (2M BYTES)
RESERVED
SCRATCHPAD SRAM (4K BYTES)
RESERVED
INSTRUCTION BANK C SRAM/CACHE (16K BYTES)
RESERVED
INSTRUCTION BANK B SRAM (16K BYTES)
INSTRUCTION BANK A SRAM (16K BYTES)
RESERVED
DATA BANK B SRAM / CACHE (16K BYTES)
DATA BANK B SRAM (16K BYTES)
RESERVED
DATA BANK A SRAM / CACHE (16K BYTES)
DATA BANK A SRAM (16K BYTES)
RESERVED
BOOT ROM (32K BYTES)
RESERVED
ASYNC MEMORY BANK 3 (1M BYTES)
ASYNC MEMORY BANK 2 (1M BYTES)
ASYNC MEMORY BANK 1 (1M BYTES)
ASYNC MEMORY BANK 0 (1M BYTES)
RESERVED
SDRAM MEMORY (16M BYTES - 128M BYTES)
Figure 3. ADSP-BF51x Internal/External Memory Map
The on-chip L1 memory system is the highest-performance
memory available to the Blackfin processor. The off-chip mem-
ory system, accessed through the external bus interface unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132M bytes of
physical memory.
The memory DMA controller provides high bandwidth data-
movement capability. It can perform block transfers of code or
data between the internal memory and the external
memory spaces.
Internal (On-Chip) Memory
The ADSP-BF51x processors have three blocks of on-chip
memory that provide high bandwidth access to the core.
The first block is the L1 instruction memory, consisting of
48K bytes SRAM, of which 16K bytes can be configured as a
four-way set-associative cache. This memory is accessed at full
processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of up to two banks of up to 32K bytes each. Each memory
bank is configurable, offering both cache and SRAM functional-
ity. This memory block is accessed at full processor speed.
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
The SDRAM controller can be programmed to interface to up
to 128M bytes of SDRAM. A separate row can be open for each
SDRAM internal bank, and the SDRAM controller supports up
to four internal SDRAM banks, improving overall performance.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1M byte segment regardless of the size of the devices used, so
that these banks are only contiguous if each is fully populated
with 1M byte of memory.
Flash Memory
The ADSP-BF51xF processors contain an SPI flash memory
within the package of the processor connected to SPI0
(Figure 4).
The SPI flash memory has a 16M bit capacity. Also included are
support for software write protection and for fast erase and
byte-program.
Rev. D | Page 5 of 68 | April 2014
5 Page 
ADSP-BF512/BF514/BF514F16/BF516/BF518/BF518F16
10/100 Ethernet MAC
The ADSP-BF516 and ADSP-BF518/ADSP-BF518F16 proces-
sors offer the capability to directly connect to a network by way
of an embedded fast Ethernet media access controller (MAC)
that supports both 10-BaseT (10M bits/sec) and 100-BaseT
(100M bits/sec) operation. The 10/100 Ethernet MAC periph-
eral on the processor is fully compliant to the IEEE 802.3-2002
standard and it provides programmable features designed to
minimize supervision, bus use, or message processing by the
rest of the processor system.
Some standard features are:
• Support of MII and RMII protocols for external PHYs
• Full duplex and half duplex modes
• Data framing and encapsulation: generation and detection
of preamble, length padding, and FCS
• Media access management (in half-duplex operation): col-
lision and contention handling, including control of
retransmission of collision frames and of back-off timing
• Flow control (in full-duplex operation): generation and
detection of pause frames
• Station management: generation of MDC/MDIO frames
for read-write access to PHY registers
• Operating range for active and sleep operating modes, see
Table 43 on Page 47 and Table 44 on Page 48
• Internal loopback from transmit to receive
Some advanced features are:
• Buffered crystal output to external PHY for support of a
single crystal system
• Automatic checksum computation of IP header and IP
payload fields of Rx frames
• Independent 32-bit descriptor-driven receive and transmit
DMA channels
• Frame status delivery to memory through DMA, including
frame completion semaphores for efficient buffer queue
management in software
• Tx DMA support for separate descriptors for MAC header
and payload to eliminate buffer copy operations
• Convenient frame alignment modes support even 32-bit
alignment of encapsulated receive or transmit IP packet
data in memory after the 14-byte MAC header
• Programmable Ethernet event interrupt supports any com-
bination of:
• Selected receive or transmit frame status conditions
• PHY interrupt condition
• Wakeup frame detected
• Selected MAC management counter(s) at half-full
• DMA descriptor error
• 47 MAC management statistics counters with selectable
clear-on-read behavior and programmable interrupts on
half maximum value
• Programmable receive address filters, including a 64-bin
address hash table for multicast and/or unicast frames, and
programmable filter modes for broadcast, multicast, uni-
cast, control, and damaged frames
• Advanced power management supporting unattended
transfer of receive and transmit frames and status to/from
external memory via DMA during low power sleep mode
• System wakeup from sleep operating mode upon magic
packet or any of four user-definable wakeup frame filters
• Support for 802.3Q tagged VLAN frames
• Programmable MDC clock rate and preamble suppression
• In RMII operation, seven unused signals may be config-
ured as GPIO signals for other purposes
IEEE 1588 Support
The IEEE 1588 standard is a precision clock synchronization
protocol for networked measurement and control systems. The
ADSP-BF518/ADSP-BF518F16 processors include hardware
support for IEEE 1588 with an integrated precision time proto-
col synchronization engine (PTP_TSYNC). This engine
provides hardware assisted time stamping to improve the accu-
racy of clock synchronization between PTP nodes. The main
features of the PTP_SYNC engine are:
• Support for both IEEE 1588-2002 and IEEE 1588-2008 pro-
tocol standards
• Hardware assisted time stamping capable of up to 12.5 ns
resolution
• Lock adjustment
• Programmable PTM message support
• Dedicated interrupts
• Programmable alarm
• Multiple input clock sources (SCLK, MII clock, external
clock)
• Programmable pulse per second (PPS) output
• Auxiliary snapshot to time stamp external events
Ports
Because of the rich set of peripherals, the processors group the
many peripheral signals to four ports—port F, port G, port H,
and port J. Most of the associated pins/balls are shared by multi-
ple signals. The ports function as multiplexer controls.
General-Purpose I/O (GPIO)
The ADSP-BF51x processors have 40 bidirectional, general-
purpose I/O (GPIO) signals allocated across three separate
GPIO modules—PORTFIO, PORTGIO, and PORTHIO, associ-
ated with Port F, Port G, and Port H, respectively. Each
GPIO-capable signal shares functionality with other peripherals
via a multiplexing scheme; however, the GPIO functionality is
the default state of the device upon power-up. Neither GPIO
output nor input drivers are active by default. Each general-pur-
pose port signal can be individually controlled by manipulation
of the port control, status, and interrupt registers.
Rev. D | Page 11 of 68 | April 2014
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADSP-BF518.PDF ] | |
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