DataSheetWiki


ADSP-SC572 fiches techniques PDF

Analog Devices - SHARC+ Dual Core DSP

Numéro de référence ADSP-SC572
Description SHARC+ Dual Core DSP
Fabricant Analog Devices 
Logo Analog Devices 





1 Page

No Preview Available !





ADSP-SC572 fiche technique
SHARC+ Dual Core
DSP with ARM Cortex-A5
Preliminary Technical Data ADSP-SC570/571/572/573/ADSP-21571/21573
SYSTEM FEATURES
Dual enhanced SHARC+ high performance floating-point
cores
Up to 450 MHz per SHARC+ core
Up to 3M bits (384 kB) L1SRAM memory per core with
parity (optional ability to configure as cache)
32-bit, 40-bit, and 64-bit floating-point support
32-bit fixed point
Byte, short-word, word, long-word addressed
ARM Cortex-A5 core
450 MHz/720 DMIPS with Neon/VFPv4-D16/Jazelle
32 kB L1 instruction cache with parity/32 kB L1 data cache
with parity
256 kB L2 cache with parity
Powerful DMA system
On-chip memory protection
Integrated safety features
17 mm × 17 mm 400-ball CSP BGA and 176-lead LQFP-EP,
RoHS compliant
Low system power across automotive temperature range
MEMORY
Large on-chip L2 SRAM with ECC protection, up to 1MB
One L3 interface optimized for low system power, providing
16-bit interface to DDR3, DDR2 or LPDDR1 SDRAM devices
ADDITIONAL FEATURES
Security and Protection
Crypto hardware accelerators
Fast secure boot with IP protection
Support for TrustZone®
Accelerators
FIR, IIR, offload engines
SYSTEM CONTROL
SECURITY AND PROTECTION
SYSTEM PROTECTION (SPU)
SYSTEM MEMORY
PROTECTION UNIT (SMPU)
FAULT MANAGEMENT
ARM® TrustZone® SECURITY
DUAL CRC
WATCHDOGS
OTP MEMORY
THERMAL MONITOR UNIT (TMU)
PROGRAM FLOW
SYS EVENT CONTROLLER (SEC)
TRIGGER ROUTING (TRU)
CLOCK, RESET, AND POWER
CLOCK GENERATION (CGU)
CLOCK DISTRIBUTION
UNIT (CDU)
RESET CONTROL (RCU)
POWER MANAGEMENT (DPM)
DEBUG UNIT
ARM® CoreSightTM
WATCHPOINTS (SWU)
CORE 0
L1 CACHE (PARITY)
32 kB L1 I-CACHE
32 kB L1 D-CACHE
L2 CACHE
256 kB (PARITY)
CORE 1
S
L1 SRAM (PARITY)
3M BITS (384 kB)
SRAM/CACHE
CORE 2
S
L1 SRAM (PARITY)
3M BITS (384 kB)
SRAM/CACHE
SYSTEM CROSSBAR AND DMA SUBSYSTEM
L3 MEMORY
INTERFACE
DDR3
DDR2
LPDDR1
16
DATA
SYSTEM
L2 MEMORY
L2 SRAM
8M BITS (1MB)
L2 SRAM (ECC)
SYSTEM
ACCELERATION
DSP FUNCTIONS
(FIR, IIR)
ENCRYPTION/DECRYPTION
PERIPHERALS
SRU
2× PRECISION CLOCK
GENERATORS
ASRC FULL SPORT
4× PAIRS
0-3
1x DAI
1x PIN
BUFFER
1× S/PDIF Rx/Tx
3× I2C
2× LINK PORTS
2× SPI + 1× QUAD SPI
3× UARTs
1× EPPI
8× TIMERS + 1× COUNTER
ADC CONTROL MODULE
(ACM)
ASYNC MEMORY (16-BIT)
2× CAN2.0
SD/SDIO/eMMC
MLB 3-PIN
1× EMAC
8x SHARC FLAGS
G
P
I
O
1 USB 2.0 HS
MLB 6-PIN
HADC (8 CHAN, 12-BIT)
Figure 1. Processor Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.; SHARC+ is a trademark of Analog Devices, Inc.
Rev. PrB
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

PagesPages 30
Télécharger [ ADSP-SC572 ]


Fiche technique recommandé

No Description détaillée Fabricant
ADSP-SC570 SHARC+ Dual Core DSP Analog Devices
Analog Devices
ADSP-SC571 SHARC+ Dual Core DSP Analog Devices
Analog Devices
ADSP-SC572 SHARC+ Dual Core DSP Analog Devices
Analog Devices
ADSP-SC573 SHARC+ Dual Core DSP Analog Devices
Analog Devices

US18650VTC5A

Lithium-Ion Battery

Sony
Sony
TSPC106

PCI Bus Bridge Memory Controller

ATMEL
ATMEL
TP9380

NPN SILICON RF POWER TRANSISTOR

Advanced Semiconductor
Advanced Semiconductor


www.DataSheetWiki.com    |   2020   |   Contactez-nous  |   Recherche