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National Semiconductor - Synchronous Decade Up/Down Counters

Numéro de référence 54190
Description Synchronous Decade Up/Down Counters
Fabricant National Semiconductor 
Logo National Semiconductor 





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54190 fiche technique
January 1988
MM54HC190 MM74HC190 Synchronous
Decade Up Down Counters with Mode
Control MM54HC191 MM74HC191
Synchronous Binary Up Down Counters
with Mode Control
General Description
These high speed synchronous counters utilize advanced
silicon-gate CMOS technology They possess the high noise
immunity and low power consumption of CMOS technology
along with the speeds of low power Schottky TTL
These circuits are synchronous reversible up down count-
ers The MM54HC191 MM74HC191 are 4-bit binary count-
ers and the MM54HC190 MM74HC190 are BCD counters
Synchronous operation is provided by having all flip-flops
clocked simultaneously so that the outputs change simulta-
neously when so instructed by the steering logic This mode
of operation eliminates the output counting spikes normally
associated with asynchronous (ripple clock) counters
The outputs of the four master-slave flip-flops are triggered
on a low-to-high level transition of the clock input if the
enable input is low A high at the enable input inhibits count-
ing The direction of the count is determined by the level of
the down up input When low the counter counts up and
when high it counts down
These counters are fully programmable that is the outputs
may be preset to either level by placing a low on the load
input and entering the desired data at the data inputs The
output will change independent of the level of the clock in-
put This feature allows the counters to be used as modulo-
N dividers by simply modifying the count length with the
preset inputs
Two outputs have been made available to perform the cas-
cading function ripple clock and maximum minimum count
The latter output produces a high-level output pulse with a
duration approximately equal to one complete cycle of the
clock when the counter overflows or underflows The ripple
clock output produces a low-level output pulse equal in
width to the low-level portion of the clock input when an
overflow or underflow condition exists The counters can be
easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel clocking is
used or to the clock input if parallel enabling is used The
maximum minimum count output can be used to accom-
plish look-ahead for high-speed operation
Features
Y Level changes on Enable or Down Up can be made re-
gardless of the level of the clock input
Y Wide power supply range 2 – 6V
Y Low quiescent supply current 80 mA maximum
(74HC Series)
Y Low input current 1 mA maximum
Connection Diagram
Dual-In-Line Package
Load
H
H
L
H
Enable
G
L
L
X
H
Down
Up
L
H
X
X
Clock Function
u Count Up
u Count Down
X Load
X No Change
Asynchronous inputs Low input to load sets QA e A
QB e B QC e C and QD e D
Order Number MM54HC190 191 or MM74HC190 191
Top View
C1995 National Semiconductor Corporation TL F 5322
TL F 5322 – 1
RRD-B30M105 Printed in U S A

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