|
|
PDF CLC405 Data sheet ( Hoja de datos )
| Número de pieza | CLC405 | |
| Descripción | Low-Cost/ Low-Power/ 110MHz Op Amp with Disable | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CLC405 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
|
No Preview Available !
N
June 1999
CLC405
Low-Cost, Low-Power, 110MHz Op Amp with Disable
General Description
The CLC405 is a low-cost, wideband (110MHz) op amp featur-
ing a TTL-compatible disable which quickly switches off in 18ns
and back on in 40ns. While disabled, the CLC405 has a very high
input/output impedance and its total power consumption drops to
a mere 8mW. When enabled, the CLC405 consumes only 35mW
and can source or sink an output current of 60mA. These
features make the CLC405 a versatile, high-speed solution for
demanding applications that are sensitive to both power and cost.
Utilizing National’s proven architectures, this current feedback
amplifier surpasses the performance of alternative solutions and
sets new standards for low power at a low price. This power-
conserving op amp achieves low distortion with -72dBc and
-70dBc for second and third harmonics respectively. Many high
source impedance applications will benefit from the CLC405’s
6MΩ input impedance. And finally, designers will have a bipolar
part with an exceptionally low 100nA non-inverting bias current.
With 0.1dB flatness to 50MHz and low differential gain and phase
errors, the CLC405 is an ideal part for professional video
processing and distribution. However, the 110MHz -3dB band-
width (Av = +2) coupled with a 350V/µs slew rate also make the
CLC405 a perfect choice in cost-sensitive applications such as
video monitors, fax machines, copiers, and CATV systems.
Features
s Low-cost
s Very low input bias current: 100nA
s High input impedance: 6MΩ
s 110MHz -3dB bandwidth (Av = +2)
s Low power: Icc = 3.5mA
s Ultra-fast enable/disable times
s High output current: 60mA
Applications
s Desktop video systems
s Multiplexers
s Video distribution
s Flash A/D driver
s High-speed switch/driver
s High-source impedance applications
s Peak detector circuits
s Professional video processing
s High resolution monitors
Frequency Response (Av = +2V/V)
Typical Application
Wideband Digitally Controlled
Programmable Gain Amplifier
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
Pinout
DIP & SOIC
http://www.national.com
1 page  
Input - Bias Current, Impedances, and Source
Termination Considerations
The CLC405 has:
• a 6MΩ non-inverting input impedance.
• a 100nA non-inverting input bias current.
If a large source impedance application is considered,
remove all parasitic capacitance around the non-invert-
ing input and source traces. Parasitic capacitances
near the input and source act as a low-pass filter and
reduce bandwidth.
Current feedback op amps have uncorrelated input
bias currents. These uncorrelated bias currents prevent
source impedance matching on each input from can-
celing offsets. Refer to application note OA-07 of the
data book to find specific circuits to correct DC offsets.
Layout Considerations
Whenever questions about layout arise, USE THE
EVALUATION BOARD AS A TEMPLATE.
Use the CLC730013 and CLC730027 evaluation
boards for the DIP and SOIC respectively. These board
layouts were optimized to produce the typical perfor-
mance of the CLC405 shown in the data sheet. To
reduce parasitic capacitances, the ground plane was
removed near pins 2, 3, and 6. To reduce series induc-
tance, trace lengths of components and nodes were
minimized.
Parasitics on traces degrade performance. Minimize
coupling from traces to both power and ground planes.
Use low inductive resistors for leaded components.
Do not use dip sockets for the CLC405 DIP amplifiers.
These sockets can peak the frequency domain
response or create overshoot in the time domain
response. Use flush-mount socket pins when socket-
ing is necessary. The 730013 circuit board device
holes are sized for Cambion P/N 450-2598 socket pins
or their functional equivalent.
Insert the back matching resistor (Rout) shown in Figure
2 when driving coaxial cable or a capacitive load. Use
the plot in the typical performance section labeled
“Settling Time vs. Capacitive Load” to determine the
optimum resistor value for Rout for different capacitive
loads. This optimal resistance improves settling tim for
pulse-type applications and increases stability.
SMA
Input
Rin
50Ω
+5V
C1 C3 +
3
2
+7
CLC405
-
0.1µfd 6.8µfd
6 Rout
50Ω
SMA
Output
4 Rf
Rg
348Ω
348Ω
C2
0.1µfd
C4
6.8µfd
-5V
+
Figure 2
Use power-supply bypassing capacitors when operat-
ing this amplifier. Choose quality 0.1µF ceramics for C1
and C2. Choose quality 6.8µF tantalum capacitors for
C3 and C4. Place the 0.1µF capacitors within 0.1 inch-
es from the power pins. Place the 6.8µF capacitors
within 3/4 inches from the power pins.
Video Performance vs. IEX
Improve the video performance of the CLC405 by
drawing extra current from the amplifier output stage.
Using a single external resistor as shown in Figure 3,
you can adjust the differential phase. Video perfor-
mance vs. IEX is illustrated below in Graph 1. This graph
represents positive video performance with negative
synchronization pulses.
Differential Gain & Phase vs. IEX
0.25
0.25
0.20
Phase
0.15
0.20
0.15
0.10 0.10
0.05
0
0
0.05
Gain
0
2 4 6 8 10 12 14 16 18
IEX in mA
Graph1
Vin +
+5V
Rt CLC405
Rout Vout
-
Rf
Rpull
down
Extra I
Rg -5V -Vcc
Figure 3
The value for Rpd in Figure 3 is determined by :
at +5V supplies.
Rpd
=
5
IEX
Wideband Digital PGA
As shown on the front page, the CLC405 is easily con-
figured as a digitally controlled programmable gain
amplifier. Make a PGA by configuring several amplifiers
at required gains. Keep Rf near 348Ω and change Rg
for each different gain. Use a TTL decoder that has
enough outputs to control the selection of different gains
and the buffer stage. Connect the buffer stage like the
buffer of the front page. The buffer isolates each gain
stage from the load and can produce a gain of zero for
a gain selection of zero. Use of an inverter (7404) on the
buffer disable pin to keep the buffer operational at all
gains except zero. Or float the buffer disable pin for a
continuous enable state.
5 http://www.national.com
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet CLC405.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CLC40 | Fllstandssensoren Schaltverstarker Baureihe CLC |  ETC |
| CLC40-L05 | Fllstandssensoren Schaltverstarker Baureihe CLC | ETC |
| CLC40-L15 | Fllstandssensoren Schaltverstarker Baureihe CLC | ETC |
| CLC40-L50 | Fllstandssensoren Schaltverstarker Baureihe CLC | ETC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |