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PDF MACH221-7 Data sheet ( Hoja de datos )
| Número de pieza | MACH221-7 | |
| Descripción | High-Performance EE CMOS Programmable Logic | |
| Fabricantes | Vantis | |
| Logotipo |  |
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1
FINAL
MACH 1 & 2 FAMILIES
COM’L: -7/10/12/15
IND: -10/-12/14/18
MACH221-7/10/12/15
High-Performance EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
x 68 Pins in PLCC
x 96 Macrocells
x 7.5 ns tPD Commercial, 10 ns tPD Industrial
x 133 MHz fCNT
x 48 I/Os; 4 dedicated inputs; 4 dedicated inputs/clocks
x 96 Flip-flops; 4 clock choices
x 8 “PALCE26V12" blocks with buried macrocells
x SpeedLocking™ for guaranteed fixed timing
x Bus-Friendly™ Inputs and I/Os
x Peripheral Component Interconnect (PCI) compliant (-7/-10/-12)
x Programmable power-down mode
GENERAL DESCRIPTION
The MACH221 is a member of Vantis’ high-performance EE CMOS MACH® 1 & 2 families. This
device has approximately nine times the logic macrocell capability of the popular PALCE22V10
without loss of speed.
The MACH221 consists of eight PAL® blocks interconnected by a programmable switch matrix. The
eight PAL blocks are essentially “PALCE26V12" structures complete with product-term arrays,
programmable macrocells, which can be programmed as high speed or low power, and buried
macrocells. The switch matrix connects the PAL blocks to each other and to all input pins,
providing a high degree of connectivity between the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
The MACH221 has two kinds of macrocell: output and buried. The output macrocell provides
registered, latched, or combinatorial outputs with programmable polarity. If a registered
configuration is chosen, the register can be configured as D-type or T-type to help reduce the
number of product terms. The register type decision can be made by the designer or by the
software. All output macrocells can be connected to an I/O cell. If a buried macrocell is desired,
the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as
an input.
The MACH221 has dedicated buried macrocells which, in addition to the capabilities of the output
macrocell, also provide input registers for use in synchronizing signals and reducing setup time
requirements.
Publication# 20157 Rev: C
Amendment/0
Issue Date: August 1997
1
1 page  
VANTIS
ORDERING INFORMATION
Commercial Products
Vantis’ programmable logic products for commercial applications are available with several ordering options. The order number
(Valid Combination) is formed by a combination of:
MACH 221 -7 J C
FAMILY TYPE
MACH = Macro Array CMOS High-Speed
DEVICE NUMBER
221 = 96 Macrocells, 68 pins
SPEED
-7 = 7.5 ns tPD
-10 = 10 ns tPD
-12 = 12 ns tPD
-15 = 15 ns tPD
OPERATING CONDITIONS
C = Commercial (0°C to +70°C)
PACKAGE TYPE
J = 68-Pin Plastic Leaded
Chip Carrier (PL 068)
Valid Combinations
MACH221-7
MACH221-10
MACH221-12
JC
MACH221-15
Valid Combinations
The Valid Combinations table lists configurations planned to
be supported in volume for this device. Consult the local
Vantis sales office to confirm availability of specific valid
combinations and to check on newly released combinations.
MACH221-7/10/12/15 (Com’l)
5
5 Page 
VANTIS
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter
Description
Test Conditions
Typ Unit
CIN
Input Capacitance
VIN = 2.0 V
VCC = 5.0 V, TA = 25°C
6
pF
COUT
Output Capacitance
VOUT = 2.0 V f = 1 MHz
8 pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
-7 -10 -12 -15
Min Max Min Max Min Max Min Max Unit
tPD
Input, I/O, or Feedback to Combinatorial Output
(Note 3)
7.5 10
12
15 ns
ts
Setup Time from Input, I/O, or
Feedback to Clock (Note 3)
D-type
T-type
5.5
6.5
6.5
7.5
7
8
10
11
ns
ns
tH
tCO
tWL
tWH
fMAX
Register Data Hold Time
Clock to Output (Note 3)
Clock
LOW
Width
HIGH
Maximum
Frequency
(Note 1)
External
Feedback
D-type
1/(tS + tCO)
T-type
D-type
Internal Feedback (fCNT)
T-type
0
3
3
95
87
133
125
0 0 0 ns
56
8 10 ns
5 6 6 ns
5 6 6 ns
80 66.7 50 MHz
74 62.5 47.6 MHz
100 83.3 66.6 MHz
91 76.9 62.5 MHz
No
Feedback
1/(tWL + tWH)
166.7 100 83.3 83.3 MHz
tSL Setup Time from Input, I/O, or Feedback to Gate 5.5 6.5 7 10 ns
tHL Latch Data Hold Time
0 0 0 0 ns
tGO Gate to Output
7 7 10 11 ns
tGWL
Gate Width LOW
3 5 6 6 ns
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
9.5 12 14 17 ns
tSIR Input Register Setup Time
2 2 2 2 ns
tHIR Input Register Hold Time
2 2 2 2.5 ns
tICO Input Register Clock to Combinatorial Output
11 13 15 18 ns
tICS
Input Register Clock to Output Register D-type
Setup
T-type
9
10
10 12
11 13
15
16
ns
ns
tWICL
Input Register
LOW
3
56
6 ns
tWICH Clock Width
HIGH
3
56
6 ns
fMAXIR
Maximum Input Register
Frequency
1/(tWICL + tWICH)
166.7
100
83.3
83.3
MHz
tSIL Input Latch Setup Time
2 2 2 2 ns
MACH221-7/10/12/15 (Com’l)
11
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