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PDF CLC016AJQ Data sheet ( Hoja de datos )
| Número de pieza | CLC016AJQ | |
| Descripción | Data Retiming PLL with Automatic Rate Selection | |
| Fabricantes | National Semiconductor | |
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July 1998
CLC016
Data Retiming PLL with Automatic Rate Selection
General Description
National’s Comlinear CLC016 is a low-cost, monolithic, data
retiming phase-locked loop (PLL) designed for high-speed
serial clock and data recovery. The CLC016 simplifies high-
speed data recovery in multi-rate systems by incorporating
auto-rate select (ARS) circuitry on chip. This function allows
the user to configure the CLC016 to recognize up to four dif-
ferent data rates and automatically adjust to provide accu-
rate, low-jitter clock and data recovery. A single resistor is
used to set each data rate anywhere between 40 Mbps and
400 Mbps. No potentiometers, crystals, or other external ICs
are required to set the rate.
The CLC016 has output jitter of only 130 pspp at a 270 Mbps
data rate and 0.25% fractional loop bandwidth. Low phase
detector output offset and low VCO injection combine to en-
sure that the CLC016 does not generate bit errors or large
phase transients in response to extreme fluctuations in data
transition density. The result is improved performance when
handling the pathological patterns inherent in the SMPTE
259M video industry standard.
The carrier detect and output mute functions may be used
together to automatically latch the outputs when no data is
present, preventing random transitions. The external loop fil-
ter allows the user to tailor the loop response to the specific
application needs. The CLC016 will operate with either +5V
or −5.2V power supplies. The serial data inputs and outputs,
as well as the recovered clock outputs, allow single- or
differential-ECL interfacing. The logic control inputs are TTL-
compatible.
Features
n Retimed data output
n Recovered clock output
n Auto and manual rate select modes
n Four user-configurable data rates
n No potentiometers required
n External loop bandwidth control
n Frequency detector for lock acquisition
n Carrier detect output
n Output MUTE function
n Single supply operation: +5V or −5.2V
n Low cost
Key Specifications
n Low jitter: 130 pspp @ 270 Mbps, 0.25% fractional loop
bandwidth (0.675 MHz)
n High data rates: 40 Mbps − 400 Mbps
n Low supply current: 100 mA, including output biasing
n Flexible fractional loop bandwidth: from 0.05% to 0.5%
Applications
n SMPTE 259M serial digital interfaces: NTSC/PAL, 4:2:2
component, 360 Mbps wide screen
n Serial digital video routing and distribution
n Clock and data recovery for high-speed data
transmission
n Re-synchronization of serial data for SONET/SDH, ATM,
CAD networks, medical and industrial imaging
DS100087-1
Order Number
CLC016ACQ
CLC016AJQ
Temperature
0˚C to +70˚C
–40˚C to +85˚C
Package
PLCC V28A
PLCC V28A
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100087
www.national.com
1 page  
Typical Performance Characteristics
DS100087-4
DS100087-5
DS100087-6
DS100087-7
DS100087-8
5
DS100087-9
www.national.com
5 Page 
Product Description (Continued)
DS100087-18
FIGURE 6. Jitter Peaking Curve
As an example, assume that the amount of jitter peaking that
can be tolerated is 0.05 dB. From the jitter peaking design
equation (or from Figure 6) the required value of α is:
α ≅ 0.05[0.134 + (0.058)(0.05)] = 0.007
Now assuming that the loop bandwidth is 644 kHz and that
the value of RBW is 500Ω, the value of CZ is:
The value of CZ also affects the acquisition performance of
the PLL. Estimate the acquisition time with the following
equation:
where tACQ x fCLK is the acquisition time in number of bit
cells.
Selecting CP
Capacitor CP establishes a high frequency pole in the loop
filter to remove high frequency spectral components from the
phase detector. The pole frequency fP is:
In general, the pole should be set at least a factor of 4 above
the PLL bandwidth, fBW. Therefore, select CP using:
For example, if RBW is 500Ω and fBW is 644 kHz, then an ap-
propriate value for CP is:
In addition, CP can affect the ability of the PLL to acquire
lock, especially at high data rates. Because of this, it is rec-
ommended to eliminate CP entirely for the condition of high
data rate (>300 Mbps) combined with narrow loop band-
width (<0.1%).
Multiple Rate Considerations
RBW establishes the fractional loop bandwidth. For a fixed
value of RBW, fBW will vary with the selected data rate. The
location of the critical frequencies fZ and fP, however, are in-
dependent of data rate.
To control jitter peaking for all multi-rate application choose:
• the value of CZ for the smallest value of fBW (which is ob-
tained at the lowest data rate).
• the value of CP for the largest value of fBW (which is ob-
tained at the highest data rate).
Loop Filter Element Summary Table
The table below summarizes the recommended loop filter el-
ement values for each of the four SMPTE 259M data rates
and a fractional loop bandwidth of 0.25%. The final row of
the table gives the recommended values for the multi-rate
case, where all four of the SMPTE rates are configured.
Data Rate
(Mbps)
143
177
270
360
143–360
fBW
(kHz)
358
443
675
900
0.25% fCLK
RBW
(Ω)
500
500
500
500
500
CZ
(µF)
0.10
0.10
0.047
0.04
0.10
CP
(pF)
200
160
100
82
82
Component Types and Tolerances
It is recommended that RBW resistors have tolerances of 1%
and temperature coefficients of ≤100 ppm/˚C. The recom-
mended capacitors are ceramic surface mount with 5% toler-
ance or better.
AUTO-RATE SELECTION
Auto Rate Mode (ARM)
This section provides more detail on the ARS sub-system
and how to use it. Figure 7 shows a detailed view of the ARS
portion of the Figure 3 block diagram
The auto-rate mode is enabled by connecting AUTO to VCC
and SER to ACQ/WR through the 1 kΩ/1 nF network. When
the VCO is not at the input data rate, SER goes high en-
abling the ARS oscillator and the Latch. The oscillator incre-
ments the 2-bit counter and causes the VCO to sequence
through the rates determined by resistor Rn (beginning at the
currently selected rate and advancing the index, n, upward).
The oscillator period (TARS) is determined by CARS. When
the VCO rate is at the input data rate, SER goes low and
ceases to increment the counter.
Choosing a value for CP larger than the value recommended
by the selection equation will introduce jitter peaking. Reduc-
ing the value of CP below that recommended by the selec-
tion equation is acceptable, but will result in some increase
in jitter. This is most noticeable with large fractional loop
bandwidths.
11
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