CLC007AJE Datasheet PDF - National Semiconductor
| Part Number | CLC007AJE | |
| Description | Serial Digital Cable Driver with Dual Complementary Outputs | |
| Manufacturers | National Semiconductor | |
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July 1998
CLC007
Serial Digital Cable Driver with Dual Complementary
Outputs
General Description
National’s Comlinear CLC007 is a monolithic, high-speed
cable driver designed for the SMPTE 259M serial digital
video data transmission standard. The CLC007 drives 75Ω
transmission lines (Belden 8281 or equivalent) at data rates
up to 400 Mbps. Controlled output rise and fall times (650 ps
typical) minimize transition-induced jitter. The output voltage
swing, typically 1.65V, set by an accurate, low-drift internal
bandgap reference, delivers an 800 mV swing to back-
matched and terminated 75Ω cable.
The CLC007’s class AB output stage consumes less power
than other designs, 195 mW with all outputs terminated, and
requires no external bias resistors. The differential inputs ac-
cept a wide range of digital signals from 200 mVp-p to ECL
levels within the specified common-mode limits. All this
make the CLC007 an excellent general purpose high speed
driver for digital applications.
The CLC007 is powered from a single +5V or −5.2V supply
and comes in an 8-pin SOIC package.
Key Specifications
n 650 ps rise and fall times
n Data rates to 400 Mbps
n 2 sets of complimentary outputs
n 200 mV differential input
n Low residual jitter (25 pspp)
Features
n No external pull-down resistors
n Differential input and output
n Low power dissipation
n Single +5V or −5.2V supply
n Replaces GS9007 in most applications
Applications
n Digital routers and distribution amplifiers
n Coaxial cable driver for digital transmission line
n Twisted pair driver
n Digital distribution amplifiers
n SMPTE, Sonet/SDH, and ATM compatible driver
n Buffer applications
DS100085-1
Connection Diagram (8-Pin SOIC)
DS100085-3
Order Number CLC007AJE
See NS Package Number M08A
Typical Application
© 1998 National Semiconductor Corporation DS100085
DS100085-2
www.national.com
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Operation (Continued)
when driving 10K ECL. Noise margins will not be affected
when interfacing to F100K since F100K is fully voltage and
temperature compensated.
DS100085-9
FIGURE 6. Output Stage
FIGURE 7. Differential Input DC Coupled Output
OUTPUT RISE AND FALL TIMES
Output load capacitance can significantly affect output rise
and fall times. The effect of load capacitance, stray or other-
wise, may be reduced by placing the output back-match re-
sistor close to the output pin and by minimizing all intercon-
necting trace lengths. Figure 8 shows the effect on risetime
of parallel load capacitance across a 150Ω load.
DS100085-10
5 www.national.com
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