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PDF CLC001AJE Data sheet ( Hoja de datos )

Número de pieza CLC001AJE
Descripción Serial Digital Cable Driver with Adjustable Outputs
Fabricantes National Semiconductor 
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No Preview Available ! CLC001AJE Hoja de datos, Descripción, Manual

March 2001
CLC001
Serial Digital Cable Driver with Adjustable Outputs
General Description
The CLC001 is a monolithic, high-speed cable driver
designed for use in SMPTE 259M serial digital video and
ITU-T G.703 serial digital data transmission applications.
The CLC001 drives 75transmission lines (Belden 8281 or
equivalent) at data rates up to 622 Mbps. Controlled output
rise and fall times (400 ps typical) minimize transition-
induced jitter. The output voltage swing is adjustable from
800 mVp-p to 1.0 Vp-p using an external resistor.
The CLC001’s output stage consumes less power than other
designs. The differential inputs accept LVDS signal levels,
LVPECL levels directly or PECL with attenuation networks.
All these make the CLC001 an excellent general purpose
high speed driver for high-speed, long distance data
transmission applications.
The CLC001 is powered from a single +3.3V supply and
comes in a small 8-pin SOIC package.
Applications
n Digital routers and distribution amplifiers
n Coaxial cable driver for digital transmission lines
n Twisted pair driver
n Serial digital video interfaces for the commercial and
broadcast industry
n SMPTE, Sonet/SDH, and ATM compatible driver
n Buffer applications
Key Specifications
n 400 ps rise and fall times
n Data rates to 622 Mbps
n 100 mV differential input threshold
n Low residual jitter
Features
n Adjustable output amplitude
n Differential input and output
n Accepts LVPECL or LVDS input swings
n Low power dissipation
n Single +3.3V supply
DS101329-10
622 Mbps Eye Pattern with STM-4 Signal Mask
Connection Diagram (8-Pin SOIC)
DS101329-2
Order Number CLC001AJE
See NS Package Number M08A
Typical Application
© 2001 National Semiconductor Corporation DS101329
DS101329-1
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CLC001AJE pdf
Device Operation
INPUT INTERFACING
Numerous input configurations exist for applying PECL,
LVPECL, and LVDS signals to the input of the CLC001.
Inputs may be single-ended or differential, AC or DC
coupled.
The VBB pin may be used to provide a DC bias voltage to
the inputs. Leave this pin as a no connect when no bias is
needed. Note that DC-coupled inputs such as direct
LVDS and LVPECL connections are self-biasing and do
not require use of the VBB pin. IBB, the current produced
by the VBB pin, depends on RREF. For a given RREF, the
IBB current will remain constant, and the bias voltage is
determined by the value of resistance, RBB, between the
VBB pin and ground. Figure 3 and Figure 4 show how RBB
corresponds to some common VBB values with RREF held
at 1.91 kand 1.5 k, respectively. Some common input
configurations are shown in Figure 5 through Figure 9.
DS101329-11
FIGURE 3. RBB vs. VBB for RREF = 1.91 k
DS101329-12
FIGURE 4. RBB vs. VBB for RREF = 1.5 k
5
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