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PDF BBT3821 Data sheet ( Hoja de datos )
| Número de pieza | BBT3821 | |
| Descripción | Octal 2.488Gbps to 3.187Gbps/Lane Retimer | |
| Fabricantes | Intersil | |
| Logotipo |  |
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®
Data Sheet
July 20, 2005
BBT3821
FN7483.2
Octal 2.488Gbps to 3.187Gbps/
Lane Retimer
• 0.13mm Pure-Digital CMOS Technology
• 1.5V Core Supply, Control I/O 2.5V Tolerant
Features
• 8 Lanes of Clock & Data Recovery and Retiming; 4 in
Each Direction
• Differential Input/Output
• Wide Operating Data Rate Range: 2.488Gbps to
3.1875Gbps, and 1.244Gbps to 1.59325Gbps
• Ultra Low-Power Operation (195mW typical per lane,
1550mW typical total consumption)
• Low Power Version Available for LX4 Applications
• 17mm Square Low Profile 192 pin 1.0mm Pitch EBGA
Package
• Compliant to the IEEE 802.3 10GBASE-LX4(WWDM),
10GBASE-CX4, and XAUI Specifications
• Reset Jitter Domain
• Meets 802.3ae and 802.3ak Jitter Requirements with
Significant Margin
• Received Data Aligned to Local Reference Clock for
Retransmission
• Increase Driving Distance
• LX4: Up to 40 inches of FR-4 Traces or 500 Meters of
MMF Fiber at 3.1875Gbps
• CX4: Over 15 meters of Compatible Cable
• Clock Compensation
• Tx/Rx Rate Matching via IDLE Insertion/Deletion up to
±100ppm Clock Difference
• Receive Signal Detect and 16 Levels of Receiver
Equalization for Media Compensation
• CML CX4 Transmission Output with 16 Settable Levels of
Pre-Emphasis, Eight on XAUI Side
• Single-Ended or Differential Input Lower-Speed Reference
Clock
• Ease of Testing
• Complete Suite of Ingress-Egress Loopbacks
• Full 802.3ae Pattern Generation and Test, including
CJPAT & CRPAT
• PRBS (both 223-1 and 13458 byte) Built-In Self Tests,
Error Flags and Count Output
• JTAG and AC-JTAG Boundary Scan
• Long Run Length (512 bit) Frequency Lock Ideal for
Proprietary Encoding Schemes
• Extensive Configuration and Status Reporting via 802.3
Clause 45 Compliant MDC/MDIO Serial Interface
• Automatic Load of BBT3821 Control and all XENPAK
Registers from EEPROM or DOM Circuit
• Deskewing and Lane-to-Lane Alignment
Figure 1. FUNCTIONAL BLOCK DIAGRAM
Egress 3
Egress 2
Egress 1
Egress 0
Ingress 3
Ingress 2
Ingress 1
Ingress 0
RX0N
RX0P
Clock &
Data
Recovery
Deserializer
and Comma
Detector
8B/10B
Decoder
Receive
FIFO
Receive
Parallel
Data
8B/10B
Encoder
& Mux
TX0N
TX0P
RFCP
RFCN
Clock Multiplier
3.125G
MDIO MDC
MDIO/MDC
Register File
I2C Interface
SCL SDA
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
BBT3821
List of Tables
Table 1. VALID 10b/8b DECODER & ENCODER PATTERNS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2. DEVAD DEVICE ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3. MDIO MANAGEMENT FRAME FORMATS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4. MDIO PMA/PMD DEVAD 1 REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5. IEEE PMA/PMD CONTROL 1 REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6. IEEE PMA/PMD STATUS 1 REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7. IEEE PMA/PMD, PCS, PHY XS, SPEED ABILITY REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8. IEEE DEVICES IN PACKAGE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 9. IEEE PMA/PMD TYPE SELECT REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10. IEEE PMA/PMD STATUS 2 DEVICE PRESENT & FAULT SUMMARY REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11. IEEE TRANSMIT DISABLE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 12. IEEE PMD SIGNAL DETECT REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 13. IEEE EXTENDED PMA/PMD CAPABILITY REGISTER(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14. IEEE PACKAGE IDENTIFIER REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15. XENPAK NVR CONTROL & STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16. I2C ONE-BYTE OPERATION DEVICE ADDRESS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 17. I2C ONE-BYTE OPERATION MEMORY ADDRESS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18. I2C ONE-BYTE OPERATION READ DATA REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 19. I2C ONE-BYTE OPERATION WRITE DATA REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 20. NVR I2C OPERATION CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 21. NVR I2C OPERATION STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 22. XENPAK NVR REGISTER COPY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 23. XENPAK DIGITAL OPTICAL MONITORING (DOM) CAPABILITY REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 24. XENPAK LASI RX_ALARM CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 25. XENPAK LASI TX_ALARM CONTROL REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 26. XENPAK LASI CONTROL REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 27. XENPAK LASI RX_ALARM STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 28. XENPAK LASI TX_ALARM STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 29. XENPAK LASI STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 30. XENPAK DOM TX_FLAG CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 31. XENPAK DOM RX_FLAG CONTROL REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 32. XENPAK DOM ALARM & WARNING THRESHOLD REGISTERS COPY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 33. XENPAK DOM MONITORED A/D VALUES REGISTER COPY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 34. XENPAK OPTIONAL DOM STATUS BITS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 35. XENPAK DOM EXTENDED CAPABILITY REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 36. XENPAK DOM ALARM FLAGS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 37. XENPAK DOM WARNING FLAGS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 38. XENPAK DOM OPERATION CONTROL AND STATUS REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 39. PMA CONTROL 2 REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 40. PMA SERIAL LOOP BACK CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 41. PMA PRE-EMPHASIS CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 42. PMA PRE-EMPHASIS CONTROL SETTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 43. PMA/PMD EQUALIZATION CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 44. PMA SIG_DET AND LOS DETECTOR STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 45. PMA/PMD MISCELLANEOUS ADJUSTMENT REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 46. PMA/PMD/PCS/PHY XS SOFT RESET REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
15
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5 Page 
BBT3821
data is detected in all four lanes within the span of the
Alignment FIFO, the deskewing (lane to lane) alignment
operation is performed, and will be held until another ||A|| or
IDLE-to- non-IDLE transition is detected again on the lanes.
During this alignment, up to four code groups may be
deleted on any lane. For correct operation, the XAUI Lane 0
signals should be connected to the BBT3821 Lane 0 pins.
The deskew algorithm state machines (each implemented
according to IEEE 802.3ae) are enabled by setting the
DSKW_SM_EN bits (Address [3,4].C000’h, see Table 63
and/or Table 80) to 1 or overriding them with the respective
XAUI_EN bits in the [3,4].C001’h registers (Table 64 and
Table 81). Note that when one side’s DSKW_SM_EN is set
to 1, the same side CAL_EN bit (Address [3,4].C000’h,
Table 63/Table 80) is ignored. When a DSKW_SM_EN bit is
set to 0, lane deskew can still be enabled by setting
CAL_EN, but the deskew action will be carried out without
hysteresis.
The user has the option to disable trunking, or to enable
trunking across each set of 4 lanes, in the PCS (device 3)
and PHY XGXS (device 4), under control of the respective
PSYNC bits in registers [3,4].C000h. In trunking mode, the
lanes may have phase differences, but they are expected to
be frequency synchronous. In non-trunking mode, each
received serial stream need only be within ±100ppm of the
nominal bit rate (2.488Gbps to 3.1875Gbps in full-speed
mode or 1.244Gbps to 1.59375Gbps in half-speed mode).
Setting the PSYNC bits high will enable the trunking mode,
so that all transmitted data will be synchronized to the same
clock. Note that trunking mode is only possible if 8B/10B
Coding is activated, and all lanes have the same half-rate
setting (See Table 71).
Clock Compensation
In addition to deskew, the Receive FIFOs also compensate
for clock differences. Since the received serial streams can,
under worst case conditions, be off by up to ±200ppm from
the local clock domain, the received data must be adjusted
to the local reference clock frequency.
Another 8 bytes of RXFIFO are dedicated for clock
compensation. The FIFOs achieve clock tolerance by
identifying any of the IDLE patterns (/K/, /A/ or /R/ as defined
by the IEEE 802.3ae standard) in the received data and then
adding or dropping IDLEs as needed. The Receive FIFO
does not store the actual IDLE sequences received but
generates the number of IDLEs needed to compensate for
clock tolerance differences. The IDLE patterns retransmitted
will be determined according to the IEEE 802.3ae algorithm
if the appropriate AKR_SM_EN bit is set in Registers
[3,4].C001’h (see Table 64 and Table 81).
Transmitter Operations
8b/10b Encoding
The internal 10b encoding specified in the IEEE802.3-2002
specification, section 36.2.4 in Tables 36-1 & 36-2, and
discussed in more detail in “8b/10b Coding and Decoding”
page 12, is enabled by default in the PCS and PHY XS
through the setting of the respective CODECENA bits to 1’b,
and may be disabled through the MDIO registers
[3,4].C000’h (see Table 63 and Table 80) by setting the
respective bit to 0’b. Note that the receive decoding will also
be disabled. The (decoded, synchronized and aligned) data
is transferred via the transmit FIFOs, (normally) encoded,
serialized and re-transmitted on the Serial Output pins,
whose effective output impedance is nominally 100Ω
differential.
Pre-Emphasis
In order to compensate for the loss of the high frequency
signal component through PCB traces or the CX4 Cable
Assembly, sixteen levels of programmable pre-emphasis
have been provided on the CX4/LX4 PMA serial transmit
lanes, and eight levels on the XAUI PHY XS serial transmit
lanes. The output signal is boosted immediately after any
transition (see Figure 3). This maximizes the data eye
opening at the receiver inputs and enhances the bit error
rate performance of the system. The MDIO Registers at
Addresses [1,4].C005’h (see Table 41 and Table 85) control
the level of pre-emphasis for the PMA/PMD (sixteen levels)
and PHY XGXS (eight levels) respectively, settable from
none to the maximum. The initial default values of the
PMA/PMD register depend on the LX4_MODE configuration
pin, and are set to the optimum values for CX4 or XAUI
(assumed best for LX4 drivers). Both these registers may be
auto-loaded (see Auto-Configuring Control Registers
page 16) from an NVR EEPROM on start-up or RESET.
FIGURE 3. PRE-EMPHASIS OUTPUT ILLUSTRATION
1100
VLOW-pp
VHI-pp
Bit
Time
Bit
Time
Bit
Time
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet BBT3821.PDF ] | |
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