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PDF BBT3420 Data sheet ( Hoja de datos )
| Número de pieza | BBT3420 | |
| Descripción | Quad 2.488-3.1875Gbps/Channel Transceiver | |
| Fabricantes | Intersil | |
| Logotipo |  |
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®
Data Sheet
September 14, 2005
BBT3420
FN7481.1
Quad 2.488-3.1875Gbps/Channel Transceiver
1 Features
• Four channels of transmitter and receiver with serial data
transfer rates of 2.488-3.1875Gbps/channel with full rate
and half-rate operations
• Up to 12.75Gbps data rate at full duplex
• User-controlled dual-speed operation (per channel) 2.488-
3.1875Gbps or 1.244-1.59Gbps
• IEEE 802.3ae-2002 10 GE and 10 GFC compliant
- XAUI, XGMII, and MDC/MDIO interfaces
• XGMII format 10-bit parallel input/output data
- Supports HSTL 1.8V and 2.5V SSTL_2
• Extensive configuration via 802.3-compliant MDC/MDIO
serial interface
• 8bit/10bit Encoding/Decoding per channel with selectable
parallel input/output data sizes
- Support optional 8b/10b encoder/decoder bypass
operation
• Integrated Equalization and Pre-emphasis
• De-skewing and channel-to-channel alignment options
• Low power, 250mW per channel typical
• Meets jitter requirements with significant margin
• Comma detection and synchronization, byte alignment
• Tx/Rx rate matching via IDLE insertion/deletion
• Receive signal detect and 16 levels of transmission
medium equalization
• CML transmit outputs with four levels of pre-emphasis
• Loopback
- Per-channel serial Tx-to-Rx and Rx-to-Tx parallel
internal loopback modes
• Single-ended/differential input Reference clock
• Double Data-Rate (DDR) mode, also optional SDR (Single
Data Rate) on transmitter
• Support both source-centered and source-simultaneous
clocking
• Long Run Length (512 bit) frequency lock ideal for
proprietary encoding schemes Transmit byte clock
schemes
- One Transmit Byte Clock (TBC) for each channel, or
one TBC for all four channels
• Received clock schemes
- Receive data aligned to local reference clock, to
recovered clock for each channel, or to recovered clock
for Channel A only
• Supports Built-In Self Test (BIST) and IEEE 1149.1 JTAG
• On-chip 25Ω series output terminations (XGMII side)
• Standard 0.18µm 1.8V CMOS technology
• 3.3V tolerant I/O
Switch Card
nPower BBT 3420
Transceiver
XAUI
Up to 40"
nPower BBT 3420
Transceiver
XGMII
Serial 10 Gigabit
10GBASE-R
Custom ASIC
&
MAC Functions
XGMII
nPower BBT 3420
Transceiver
XXAAUUII
Optical
Transponder
Switch
Fabric
nPower BBT 3420
Transceiver
XAUI
Up to 40"
nPower BBT 3420
Transceiver
XGMII
WDM 10 Gigabit
10GBASE-LX4
Custom ASIC
&
MAC Functions
XGMII
nPower BBT 3420
Transceiver
XXAAUUII
WDM
Optical
Transponder
FIGURE 1-1. EXAMPLE BACKPLANE AND LINE CARD APPLICATIONS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
BBT3420
TABLE 3-1. VALID 8B/10B ENCODER PATTERNS (Continued)
TRANSMITTING SERDES
K-BIT
TD DATA
TRANS_EN AKR_EN BIT
BIT (Note 1) (Note 1)
SERIAL
CHARACTER
SERIAL
CODE
NOTES and
DESCRIPTION
1 FD
X X /T/
K29.7 Terminate
1 3C
XX
K28.1 Extra comma
1 5C
X X /F/
K28.2 Signal Ordered_Set marker
1 9C
X X /Q/
K28.4 Sequence Ordered_Set marker
1 DC
XX
K28.6
1 FC
XX
K28.7 Repeat gives False Comma
1 F7
XX
K23.7
1 FE
X X /E/
K30.7 Error Code
1 (all others)
X X Invalid code
Error Code
NOTES:
1. If the XAUI_EN bit is set, the BBT3420 acts as though both the TRANS_EN and AKR_EN bits are set.
2. The XGMII IDLE character is set by the XGMII IDLE register, address 1B’h/C003’h (see Table 3-26), default value 07’h, combined with the K
bit (XGMII value 107’h).
3.2 Transmit Byte Clock
3.2.1 FULL- AND HALF-RATE MODE
Since the BBT3420 normally employs Double Data Rate
(DDR) timing, the local reference clock requirement is
lowered to 124.4-159.375MHz. The Transmit Byte Clock
(TBC) must be frequency-synchronous with the local
reference clock. For any channel set to Half-Rate Clock
Mode by the MDIO/MDC register 1F’h (for Clause 22) and/or
C008’h (for Clause 45), see Table 3-30, the TBC must be
provided at half the ref clock frequency, unless the TX_SDR
bit is set in the MDIO register C001’h (Clause 45, Table 3-
33) and/or 1D’h (Clause 22, Table 3-28).
3.2.2 SOURCE-CENTERED AND -SIMULTANEOUS
MODE
For ease of ASIC timing, the BBT3420 provides the option
for the TBC to be source-simultaneous or source-centered.
In source-simultaneous mode, the ASIC is not required to
adjust the TBC signal to the center of the data window. The
internal latch clock of the BBT3420 is set to +5 serial bit
times after the rising edge of the clock (TBC or RefClock)
when the chip is reset. In source-centered mode, the
BBT3420 expects stable data, with proper setup/hold time
with respect to the TBC from the ASIC. The specific clocking
mode is selectable by the MDIO/MDC register bit SC_TBC
at address 11’h in Clause 22 format, Table 3-16, and/or
C001’h in Clause 45 format, Table 3-33.
3.2.3 TRUNKING MODE
The TBC source for each channel is determined by the
trunking mode setting of the PSYNC pin. When trunking is
turned on (PSYNC high), all four channels are latched by the
Channel A TBC on pin TCA. In non-trunking mode, each
channel is latched with its corresponding TBC pin TC[A-D]
independently. Note that PSYNC will also force trunking of
the Receive Byte Clocks (see below). Alternatively, the
TC[A-D] inputs may be driven from a common source, such
as the local reference clock.
3.3 Transmit FIFO
A 4-byte-deep input FIFO is used to accommodate any TBC
or data drift. The initial pointer value is 2 bytes, which can
accommodate ±2 byte skew between channels, as well as
drift between the TBC and the reference clock. When the
FIFO depth is at one, the transmit data is ready for output on
the next TXC.
3.4 Serializer
The serializer accepts 10-bit transmission characters and
converts them from a parallel format to a serial bit stream at
2.488-3.1875Gbps. The system designer is expected to treat
such signals on the PCB as transmission lines and to use a
controlled impedance and suitable termination.
3.5 Pre-emphasis
In order to compensate for the loss of the high-frequency
signal components through PCB or cable, four levels of
programmable pre-emphasis have been added to all serial
transmit channels. This maximizes the data eye opening at
the receiver inputs and enhances the bit error rate
performance of the system. The MDIO Register at Address
1C’h (for Clause 22) and/or C005’h (for Clause 45) (see
Table 3-27) controls the level of pre-emphasis. Note that the
formula used to determine the pre-emphasis valuse is NOT
the same as that used in the IEEE 802.3ak-2004
specification for this parameter.
5
5 Page 
BBT3420
RETIMER function. The device may be set to respond to any
one of four DEVAD values, (4, 5, 30 or 31) by controlling the
level on the MFC and MFD pins at the end of reset. These
pins are normally outputs, but become inputs when RSTN is
active, and so may be pulled to the desired value by
moderate value resistors (~5kΩ), which will not affect the
normal operation of the pins when outputs. The value on
these pins will be latched at the rising edge of RSTN. The
coding is shown in Table 3-5. A weak pullup is built into
these pins, so that if unwired, they will default to DEVAD = 5.
See Table 6-13 and Figure 6-9 for the timing of these
signals. The Clause 45-accessible registers are listed in
Table 3-7. These register addresses are independent of the
DEVAD value, including the ‘Vendor Defined’ DEVAD values
30 & 31; thus registers 30.8 & 31.8 include the RX_FAULT
and TX_FAULT bits.
Each individual device may have up to 216 (65,536)
registers. The BBT3420 implements 11 of the IEEE-defined
registers for PHY XS and DTE XS devices (they may be
accessed identically through any of the implemented DEVAD
address values), and 11 of the 32k (215) allowed Vendor
Specific registers. The latter have been placed in the block
beginning at C000’h so as to avoid the areas currently
defined as for use by the XENPAK module and similar MSA
devices, to facilitate use of the BBT3420 in systems using
such modules and/or devices.
In order to align the registers and bits as closely as possible
to the new IEEE Clause 45 standard, while maintaining
compatibility with previous versions of the part before the
Clause 45 interface was defined, which used only the
Clause 22 interface, the control and status bits are differently
distributed among the registers in the two formats. The
Clause 22 registers are listed in Table 3-6, and the Clause
45 registers in Table 3-7.
TABLE 3-6. MDIO REGISTERS IN CLAUSE 22 FORMAT
MII REGISTERS
ADDRESS
NAME
DESCRIPTION
DEFAULT
R/W DETAILS
00’h Control
Reset, Enable serial loop back mode.
2040’h
R/W Table 3-8
01’h Status
Device Present & LOS
800F’h (Note 2) RO
Table 3-9
02:3’h ID Code
Manufacturer and Device OUI & IDs
01839C5V’h RO
See (Note 1)
04’h Speed Ability
10Gbps Ability
0001’h RO Table 3-11
05’h IEEE Devices
Devices in Package, Clause 22 capable
0021’h (Note 3) RO
Table 3-12
06’h Vendor Devices
Vendor Specific Devices in Package
0000’h (Note 3) RO
Table 3-13
08’h Fault Status
Transmit & Receive Fault
8000’h (Note 2) RO/LH
Table 3-14
10’h Misc. Control 1
Channel, Comma, TX Idle, MF controls
00C0’h
R/W Table 3-15
11’h Misc. Control 2
Code, Comma, Codec, TCx controls
0140’h
R/W Table 3-16
12’h Special Control Register DC Offset & RC[A:D] phase shift control
0000’h
R/W Table 3-17
13’h Resvd2
Spare Status
0000’h RO Table 3-18
16’h ERROR
Sets XGMII ERROR Code
0FF’h
R/W
Table 3-19
17’h Loop Back
Controls Serial & Parallel Loopback
0000’h
R/W Table 3-20
18’h Receive Clock
Receive Clock Mode
0001’h
R/W Table 3-21
19’h Symbol
IDLE, Alignment and Elasticity Control
000F’h
R/W Table 3-24
1A’h Errors
Error Flags
0000’h (Note 2) RO
Table 3-25
1B’h XGMII IDLE
XGMII-side IDLE Code
0007’h
R/W Table 3-26
1C’h Boost/Pre-emp
Boost and Pre-emphasis Control
0000’h
R/W Table 3-27
1D’h
1E’h
Misc. Control 3
Internal Test
VDDQ, LOS, RC timing, /A/K/R/
0000’h
AAAA’h
R/W
R/W
Table 3-28
Table 3-29
1F’h Half Rate
Half-rate clock mode enable
0000’h
R/W Table 3-30
NOTES:
1. ‘V’ is a version number. See under “3.15 JTAG” on page 22 for a note about the version number.
2. Read value depends on status signal values. Value shown indicates ‘normal’ operation.
3. Read value depends on DEVAD setting, see Table 3-5 and Figure 6-9 for details.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet BBT3420.PDF ] | |
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