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PDF NB3H63143G Data sheet ( Hoja de datos )
| Número de pieza | NB3H63143G | |
| Descripción | Programmable Clock Generator | |
| Fabricantes | ON Semiconductor | |
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NB3H63143G
Programmable Clock
Generator with Single Ended
(LVCMOS/LVTTL) and
Differential (LVPECL/LVDS/
HCSL/CML) Outputs
www.onsemi.com
The NB3H63143G is a one−time programmable (OTP), low power
PLL−based clock generator that supports any output frequency from
8 kHz to 200 MHz. The device accepts fundamental mode parallel
resonant crystal or a single ended (LVCMOS/LVTTL) reference clock
as input. It generates either three single ended (LVCMOS/LVTTL)
1
QFN16
CASE 485AE
outputs, or one single ended output and one differential
(LVPECL/LVDS/HCSL/CML) output. The output signals can be
MARKING DIAGRAM
modulated using the spread spectrum feature of the PLL
(programmable spread spectrum type, deviation and rate) for
applications demanding low electromagnetic interference (EMI).
Individual output enable pins OE[2:0] are available to enable/disable
3H631
43Gxx
ALYWG
G
the outputs. Individual output voltage pins VDDO[2:0] are available
to independently set the output voltage of each output. Up to four
different configurations can be written into the device memory. Two
selection pins (SEL[1:0]) allow the user to select the configuration to
use. Using the PLL bypass mode, it is possible to get a copy of the
input clock on any or all of the outputs. The device can be powered
down using the Power Down pin (PD#). It is possible to program the
internal input crystal load capacitance and the output drive current
3H63143G
xx
A
L
Y
W
G
= Specific Device Code
= Specific Program Code (Default
‘00’ for Unprogrammed Part)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
provided by the device. The device also has automatic gain control
(Note: Microdot may be in either location)
(crystal power limiting) circuitry which avoids the device overdriving
the external crystal.
Features
ORDERING INFORMATION
See detailed ordering and shipping information on page 23 of
this data sheet.
• Operating Power Supply: 3.3 V ±10%, 2.5 V ±10%
• I/O Standards
• Programmable Output Drive Current for Single Ended
♦ Inputs: LVCMOS/LVTTL, Fundamental Mode
Outputs
Crystal
♦ Outputs: 1.8 V to 3.3 V LVCMOS/LVTTL
♦ Outputs: LVPECL, LVDS, HCSL and CML
• 3 Programmable Single Ended (LVCMOS/LVTTL)
Outputs from 8 kHz to 200 MHz
• 1 Programmable Differential Clock Output up to
200 MHz
• Input Frequency Range
♦ Crystal: 3 MHz to 50 MHz
• Power Saving Mode through Power Down Pin
• Programmable PLL Bypass Mode
• Programmable Output Inversion
• Programming and Evaluation Kit Available for Field
Programming and Quick Evaluation
• Temperature Range −40°C to 85°C
• Packaged in 16−pin QFN
• These are Pb−Free Devices
♦ Reference Clock: 3 MHz to 200 MHz
• Configurable Spread Spectrum Frequency Modulation
Typical Applications
• eBooks and Media Players
Parameters (Type, Deviation, Rate)
• Individual Output Enable Pins
• Independent Output Voltage Pins
• Smart Wearables, Smart Phones, Portable Medical and
Industrial Equipment
• Set Top Boxes, Printers, Digital Cameras and
• Programmable Internal Crystal Load Capacitors
Camcorders
© Semiconductor Components Industries, LLC, 2015
October, 2015 − Rev. 2
1
Publication Order Number:
NB3H63143G/D
1 page  
NB3H63143G
Clock Input
Input Frequency
The clock input block can be programmed to use
a fundamental mode crystal from 3 MHz to 50 MHz or
a single ended reference clock source from 3 MHz to
200 MHz. When using output frequency modulation for
EMI reduction, for optimal performance, it is recommended
to use crystals with a frequency greater than 6.75 MHz as
input. Crystals with ESR values of up to 150 W are
supported. While using a crystal as input, it is important to
set crystal load capacitor values correctly to achieve good
performance.
Programmable Crystal Load Capacitors
The provision of internal programmable crystal load
capacitors eliminates the necessity of external load
capacitors for standard crystals. The internal load capacitors
can be programmed to any value between 4.36 pF and
20.39 pF with a step size of 0.05 pF. Refer to Table 5 for
recommended maximum load capacitor values for stable
operation. There are three modes of loading the crystal −
with internal chip capacitors only, with external capacitors
only or with the both internal and external capacitors. Check
with the crystal vendor’s load capacitance specification for
setting of the internal load capacitors. The minimum value
of 4.36 pF internal load capacitor need to be considered
while selecting external capacitor value. The internal load
capacitors will be bypassed when using an external
reference clock.
Automatic Gain Control (AGC)
The Automatic Gain Control (AGC) feature adjusts the
gain to the input clock based on its signal strength to
maintain a good quality input clock signal level. This feature
takes care of low clock swings fed from external reference
clocks and ensures proper device operation. It also enables
maximum compatibility with crystals from different
manufacturers, processes, quality and performance. AGC
also takes care of power dissipation in the crystal; avoids
overdriving the crystal and thus extending the crystal life. In
order to calculate the AGC gain accurately and avoid
increasing the jitter on the output clocks, the user needs to
provide the crystal load capacitance as well as other crystal
parameters like ESR and shunt capacitance (C0).
Programmable Clock Outputs
Output Type and Frequency
The NB3H63143G provides three independent single
ended LVCMOS/LVTTL outputs, or one single ended
LVCMOS/LVTTL output and one LVPECL/LVDS/HCSL/
CML differential output. The device supports any single
ended output or differential output frequency from 8 kHz up
to 200 MHz with or without frequency modulation. All
outputs have individual output enable pins (refer to the
Output Enable/Disable section on page 7). It should be
noted that certain combinations of output frequencies and
spread spectrum configurations may not be recommended
for optimal and stable operation.
For differential clocking, CLK0 and CLK1 can be
configured as LVPECL, LVDS, HCSL or CML. While using
differential signaling format at the output, it is required to
use only VDDO1 as output supply and use only the OE1 pin
for the output enable function. (refer to the Application
Schematic in Figure 4). When all 3 outputs are single ended,
VDDO0 and OE0 have normal functionality.
VDDO2 ≤ VDD
Crystal or
Reference
Clock Input
XIN/CLKIN
VDDO2
CLK2
XOUT
NB3H63143G VDDO1
VDDO0
Single Ended Clock
VDDO1 ≤ VDD
CLK1
CLK0
Differential Clock
LVPECL/LVDS/HCSL/CML
OE2 OE0
PD# OE1
Figure 4. Application Setup for Differential Output Configuration
Programmable Output Drive
The drive strength or output current of each of the
LVCMOS clock outputs is programmable independently.
For each VDDO supply voltage, four distinct levels of
LVCMOS output drive strengths can be selected as
mentioned in DC Electrical Characteristics. This feature
provides further load drive and signal conditioning as per the
application requirement.
PLL BYPASS Mode
PLL Bypass mode can be used to buffer the input clock on
any of the outputs or all of the outputs. Any of the clock
outputs can be programmed to generate a copy of the input
clock.
www.onsemi.com
5
5 Page 
NB3H63143G
DC ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3 V ±10%, 2.5 V ±10%, VDDO[2:0] = 3.3 V ± 10%, 2.5 V ± 10%, 1.8 V ± 0.1 V; GND = 0 V, TA = −40°C to 85°C, Note 19)
Symbol
Parameter
Condition
Min Typ Max Unit
CML OUTPUTS (Notes 17 and 18)
IDDO_CML
fout = 100 MHz
fout = 200 MHz
5.0
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
7. Measurement taken with single ended clock outputs terminated with test load capacitance of 5 pF and 15 pF and differential clock
terminated with test load of 2 pF. See Figures 6, 7 and 12. Specifications for LVTTL are valid for VDD and VDDO 3.3 V only.
8. Measurement taken with outputs terminated with RS = 0 W, RL = 50 W, with test load capacitance of 2 pF. See Figure 8. Guaranteed by
characterization.
9. Measurement taken from single ended waveform.
10. Measured at crossing point where the instantaneous voltage value of the rising edge of CLKx+ equals the falling edge of CLKx−.
11. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points
for this measurement.
12. Defined as the total variation of all crossing voltage of rising CLKx+ and falling CLKx−. This is maximum allowed variance in the VCROSS
for any particular system.
13. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 9.
14. VOHmax = VOSmax + 1/2 VODmax.
15. VOLmax = VOSmin − 1/2 VODmax.
16. LVPECL outputs loaded with 50 W to VDDO1 − 2.0 V for proper operation.
17. Output parameters vary 1:1 with VDDO1.
18. CML outputs loaded with 50 W to VDDO1 for proper operation.
19. Parameter guaranteed by design verification not tested in production.
AC ELECTRICAL CHARACTERISTICS (VDD = 3.3 V ±10%, 2.5 V ±10%, VDDO[2:0] = 3.3 V ± 10%, 2.5 V ± 10%, 1.8 V
± 0.1 V; VDDO ≤ VDD, GND = 0 V, TA = −40°C to 85°C, Notes 19, 20, 23, 24 and 25)
Symbol
Parameter
Condition
Min Typ Max
fout Single Ended Output
Frequency
0.008
200
fMOD
Spread Spectrum Modulation
Rate
fclkin ≥ 6.75 MHz
30 130
SS
SSstep
Percent Spread Spectrum
(deviation from nominal
frequency)
Percent Spread Spectrum
Change Step Size
Down Spread
Center Spread
Down Spread Step Size
Center Spread Step Size
0 −4
0 ±3
0.25
0.125
SSCRED
Spectral Reduction,
3rd harmonic
@SS = −0.5%, fout = 100 MHz,
fclkin = 25 MHz Crystal, RES BW at
30 kHz, All Output Types
−10
tPU Stabilization Time from
Power−up
VDD = 3.3 V, 2.5 V with Frequency
Modulation ON
3.0
tPD Stabilization Time from
Power Down
Time from falling edge on PD pin to
Tri−stated Outputs (Asynchronous)
3.0
tSEL Stabilization Time from
Change of Configuration
With Frequency Modulation ON
3.0
tOE1
Output Enable Time
Time from rising edge on OE pin to
valid clock outputs (asynchronous)
2/fout
(MHz)
tOE2
Output Disable Time
Time from falling edge on OE pin to
valid clock outputs (asynchronous)
2/fout
(MHz)
Eppm
Synthesis Error
Configuration Dependent
0
Unit
MHz
kHz
%
%
%
%
dB
ms
ms
ms
ms
ms
ppm
www.onsemi.com
11
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| PDF Descargar | [ Datasheet NB3H63143G.PDF ] | |
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