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PDF 8V41N010 Data sheet ( Hoja de datos )
| Número de pieza | 8V41N010 | |
| Descripción | Clock Generator | |
| Fabricantes | Integrated Device Technology | |
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Clock Generator for Cavium Processors
8V41N010
General Description
The 8V41N010 is a PLL-based clock generator specifically designed
for Cavium Networks Octeon II processors. This high performance
device is optimized to generate the processor core reference clock,
the PCI-Express, sRIO, XAUI, SerDes reference clocks and the
clocks for both the Gigabit Ethernet MAC and PHY. The output fre-
quencies are generated from a 25MHz external input source or an
external 25MHz parallel resonant crystal. The industrial temperature
range of the 8V41N010 supports telecommunication, networking,
and storage requirements.
Pin Assignment
DATA SHEET
Features
• Eight selectable 100MHz and 156.25MHz clocks for PCI Express,
sRIO and GbE, HCSL interface levels
• One single-ended QF LVCMOS/LVTTL clock output at 50MHz
• Selectable external crystal or differential (single-ended)
input source
• Crystal oscillator interface designed for 25MHz, parallel
resonant crystal
• Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
• Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
QE0
nQE0
QE1
nQE1
GND
OE_E
nc
FSEL_C1
GND
VDDA
nc
FSEL_D1
VDD
nMR
VDDO
nc
GND
nc
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
55 36
56 35
57 34
58 33
59 32
60 8XXXXXX
61
31
30
62 29
63 8V41N010 28
64 27
65 26
66 25
67 24
68 23
69 22
70 21
71 20
72 19
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
GND
nc
nc
nQB0
QB0
VDDO_QB
OE_A
GND
nQA1
QA1
nQA0
QA0
VDDO_QA
GND
VDD
GND
QF
VDDO_QF
72-pin, 10mm x 10mm VFQFN Package
8V41N010 REVISION 1 06/30/15
1
NOTE: Exposed pad must always be connected to GND.
NOTE: Pin 1 is located at bottom left corner as shown.
©2015 Integrated Device Technology, Inc.
1 page  
8V41N010 DATA SHEET
Table 1. Pin Descriptions
Number
Name
Type
Description
65 nc Unused
No internal connection.
Selects the QDx, nQDx output frequency. LVCMOS/LVTTL interface levels.
66
FSEL_D1
Input
Pulldown 0 = 100MHz (default)
1 = 156.25MHz
67 VDD Power
Core supply.
Active LOW Master Reset. LVCMOS/LVTTL interface levels.
68
nMR
Input
Pulldown 0 = Reset. The internal dividers are reset causing the true outputs Qx to go low and
the inverted outputs nQx to go high. (default)
1 = Active. The internal dividers and the outputs are active.
69
VDDO
Power
Output supply.
70 nc Unused
No internal connection.
71
GND
Power
Power supply ground.
72 nc Unused
No internal connection.
ePAD
GND_EP
Power
Exposed pad of package. Connect to GND.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input
CLK, nCLK
Capacitance Control Pins
RPULLUP
RPULLDOWN
ROUT
Input Pullup Resistor
Input Pulldown Resistor
Output
Impedance
QF
Test Conditions
VDDO_QF = 3.465V
Minimum
Typical
2.5
6
50
50
15
Maximum
Units
pF
pF
k
k
Function Tables
Table 3A. FSEL_X Control Input Function Table
Input
Output Frequency
FSEL_X1
Q[Ax:Ex], nQ[Ax:Ex]
0 (default)
100MHz
1 156.25MHz
NOTE: FSEL_X denotes FSEL_A, _B, _C, _D, _E.
NOTE: Any two outputs operated at the same frequency will be
synchronous.
Table 3B. PLL_SEL Control Input Function Table
Input
PLL_SEL
Operation
0 PLL Bypass
1 (default)
PLL Mode
Table 3C. REF_SEL Control Input Function Table
Input
REF_SEL
Clock Source
0 CLK, nCLK
1 (default)
XTAL_IN, XTAL_OUT
Table 3D. OE_[A:E] Control Input Function Table
Input
Outputs
OE_[A:E]
Q[Ax:Ex], nQ[Ax:Ex]
0 High-Impedance
1 (default)
Enabled
REVISION 1 06/30/15
5 CLOCK GENERATOR FOR CAVIUM PROCESSORS
5 Page 
Typical Phase Noise at 156.25MHz
8V41N010 DATA SHEET
Offset Frequency (Hz)
REVISION 1 06/30/15
11 CLOCK GENERATOR FOR CAVIUM PROCESSORS
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet 8V41N010.PDF ] | |
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