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PDF XC2C64A Data sheet ( Hoja de datos )
| Número de pieza | XC2C64A | |
| Descripción | CoolRunner-II CPLD | |
| Fabricantes | Xilinx | |
| Logotipo |  |
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0
R XC2C64A CoolRunner-II CPLD
DS311 (v2.3) November 19, 2008
0 0 Product Specification
Features
• Optimized for 1.8V systems
- As fast as 4.6 ns pin-to-pin logic delays
- As low as 15 μA quiescent current
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
• Available in multiple package options
- 44-pin VQFP with 33 user I/Os
- 48-land QFN with 37 user I/Os
- 56-ball CP BGA with 45 user I/Os
- 100-pin VQFP with 64 user I/Os
- Pb-free available for all packages
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Two separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
· Optional DualEDGE triggered registers
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
macrocell
· Multiple global output enables
· Global set/reset
- Efficient control term clocks, output enables, and
set/resets for each macrocell and shared across
function blocks
- Advanced design security
- Optional bus-hold, 3-state, or weak pullup on
selected I/O pins
- Open-drain output option for Wired-OR and LED
drive
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
- PLA architecture
· Superior pinout retention
· 100% product term routability across function
block
- Hot pluggable
Refer to the CoolRunner™-II family data sheet for architec-
ture description.
Description
The CoolRunner-II 64-macrocell device is designed for both
high performance and low power applications. This lends
power savings to high-end communication equipment and
high speed to battery operated devices. Due to the low
power stand-by and dynamic operation, overall system reli-
ability is improved.
This device consists of four Function Blocks inter-connected
by a low power Advanced Interconnect Matrix (AIM). The
AIM feeds 40 true and complement inputs to each Function
Block. The Function Blocks consist of a 40 by 56 P-term
PLA and 16 macrocells which contain numerous configura-
tion bits that allow for combinational or registered modes of
operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain, and programmable grounds. A Schmitt trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers can be
configured as "direct input" registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as a
synchronous clock source. Macrocell registers can be indi-
vidually configured to power up to the zero or one state. A
global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset, and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
The CoolRunner-II 64-macrocell CPLD is I/O compatible
with standard LVTTL and LVCMOS18, LVCMOS25, and
LVCMOS33 (see Table 1). This device is also 1.5V I/O com-
patible with the use of Schmitt-trigger inputs.
Another feature that eases voltage translation is I/O bank-
ing. Two I/O banks are available on the CoolRunner-II 64A
macrocell device that permit easy interfacing to 3.3V, 2.5V,
1.8V, and 1.5V devices.
© 2004–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS311 (v2.3) November 19, 2008
Product Specification
www.xilinx.com
1
1 page  
R XC2C64A CoolRunner-II CPLD
LVCMOS 1.5V DC Voltage Specifications
Symbol
VCCIO
VT+
VT-
VOH
Parameter(1)
Input source voltage
Input hysteresis threshold voltage
High level output voltage
VOL Low level output voltage
Notes:
1. Hysteresis used on 1.5V inputs.
Test Conditions
-
-
-
IOH = –8 mA, VCCIO = 1.4V
IOH = –0.1 mA, VCCIO = 1.4V
IOL = 8 mA, VCCIO = 1.4V
IOL = 0.1 mA, VCCIO = 1.4V
Min.
1.4
0.5 x VCCIO
0.2 x VCCIO
VCCIO – 0.45
VCCIO – 0.2
-
-
Max.
1.6
0.8 x VCCIO
0.5 x VCCIO
-
-
0.4
0.2
Units
V
V
V
V
V
V
V
Schmitt Trigger Input DC Voltage Specifications
Symbol
VCCIO
VT+
VT-
Parameter
Input source voltage
Input hysteresis threshold voltage
Test Conditions
-
-
-
Min.
1.4
0.5 x VCCIO
0.2 x VCCIO
Max.
3.9
0.8 x VCCIO
0.5 x VCCIO
Units
V
V
V
DS311 (v2.3) November 19, 2008
Product Specification
www.xilinx.com
5
5 Page 
R XC2C64A CoolRunner-II CPLD
Pin Descriptions (Continued)
Function Block
Macrocell PC44(1) VQ44
QFG48
3
1
35 29
45
3
2
34 28
44
3
3
33 27
43
3 4 --
3 5 - - 39
3
6
29 23
38
3 7 --
3 8 --
3 9 - - 37
3
10
28 22
36
3
11
27 21
35
3
12
26 20
34
3 13 - -
3
14
25 19
33
3
15
24 18
32
3 16 - -
4
1
11 5
17
4
2
12 6
18
4 3 --
4 4 --
4 5 --
4 6 --
4
7
14 8
20
4 8 --
4 9 --
4 10 - - 24
4
11
18 12
25
4 12 - - 26
4
13
19 13
27
4
14
20 14
28
4 15 22 16
4 16 - - 30
1. This is an obsolete package type. It remains here for legacy support only.
2. GTS = global output enable, GSR = global set reset, GCK = global clock.
3. GCK, GSR, and GTS pins can also be used for general purpose I/Os.
CP56
C4
A4
C5
A7
C8
A8
A9
-
A5
A10
B10
C10
D8
E8
D10
-
K6
H5
K7
-
H7
-
H8
-
-
K8
H10
-
G10
-
F10
E10
VQ100
91
90
89
81
79
78
77
76
74
72
71
70
68
67
64
61
35
36
37
39
40
41
42
43
49
50
52
53
55
56
58
60
I/O Banking
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 2
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
Bank 1
DS311 (v2.3) November 19, 2008
Product Specification
www.xilinx.com
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet XC2C64A.PDF ] | |
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