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Analog Devices - SHARC+ Dual Core DSP

Numéro de référence ADSP-21584
Description SHARC+ Dual Core DSP
Fabricant Analog Devices 
Logo Analog Devices 





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ADSP-21584 fiche technique
SHARC+ Dual Core
DSP with ARM Cortex-A5
Preliminary Technical Data ADSP-SC582/583/584/587/589/ADSP-21583/584/587
SYSTEM FEATURES
Dual enhanced SHARC+ high performance floating-point
cores
Up to 450 MHz per SHARC+ core
Up to 5 Mbits (640 kB) L1SRAM memory per core with
parity (optional ability to configure as cache)
32-bit, 40-bit, and 64-bit floating-point support
32-bit fixed point
Byte, short-word, word, long-word addressed
ARM Cortex-A5 core
450 MHz/720 DMIPS with Neon/VFPv4-D16/Jazelle
32 kB L1 instruction cache/32 kB L1 data cache
256 kB L2 cache with parity
Powerful DMA system
On-chip memory protection
Integrated safety features
19 mm × 19 mm 349/529 BGA (0.8 pitch), RoHS compliant
Low system power across automotive temperature range
MEMORY
Large on-chip L2 SRAM with ECC protection, up to 256 kB
On-chip L2 ROM (512 kB)
Two L3 interfaces optimized for low system power, providing
16-bit interface to DDR3, DDR2 or LPDDR1 SDRAM devices
ADDITIONAL FEATURES
Security and Protection
Crypto hardware accelerators
Fast secure boot with IP protection
Support for TrustZone®
Accelerators
High performance pipelined FFT/IFFT engine
FIR, IIR, HAE, SINC offload engines
SYSTEM CONTROL
SECURITY AND PROTECTION
SYSTEM PROTECTION (SPU)
SYSTEM MEMORY
PROTECTION UNIT (SMPU)
FAULT MANAGEMENT
ARM® TrustZone® SECURITY
DUAL CRC
WATCHDOGS
OTP MEMORY
THERMAL SENSOR
PROGRAM FLOW
SYS EVENT CONTROLLER (SEC)
TRIGGER ROUTING (TRU)
CLOCK, RESET, AND POWER
CLOCK GENERATION (CGU)
CLOCK DISTRIBUTION
UNIT (CDU)
REAL TIME CLOCK (RTC)
RESET CONTROL (RCU)
POWER MANAGEMENT (DPM)
DEBUG UNIT
ARM® CoreSightTM
WATCHPOINTS (SWU)
CORE 0
L1 CACHE
32 kB L1 I-CACHE
32 kB L1 D-CACHE
L2 CACHE
256 kB (PARITY)
CORE 1
S
L1 SRAM (PARITY)
5M BITS (640 kB)
SRAM/CACHE
CORE 2
S
L1 SRAM (PARITY)
5M BITS (640 kB)
SRAM/CACHE
SYSTEM CROSSBAR AND DMA SUBSYSTEM
L3 MEMORY
INTERFACES
DDR3
DDR2
LPDDR1
DDR3
DDR2
LPDDR1
16
DATA
16
DATA
SYSTEM
L2 MEMORY
2M BITS (256 kB)
L2 SRAM (ECC)
4M BITS (512 kB)
2 × 2M BITS ROM
SYSTEM
ACCELERATION
DSP FUNCTIONS
(FFT/iFFT, FIR, IIR, HAE/SINC)
ENCRYPTION/DECRYPTION
Figure 1. Processor Block Diagram
PERIPHERALS
SRU
4× PRECISION CLOCK
GENERATORS
ASRC FULL SPORT
8× PAIRS
0-7
2x DAI
2x PIN
BUFFER
2× S/PDIF Rx/Tx
3× I2C
2× LINK PORTS
2× SPI + 1× QUAD SPI
3× UARTs
1× EPPI
3× ePWM
8× TIMERS + 1× COUNTER
ADC CONTROL MODULE
(ACM)
ASYNC MEMORY (16-BIT)
2× CAN2.0
SD/SDIO/eMMC
G
P
I
O
MLB 3-PIN
2× EMAC
SINC FILTER
8x SHARC FLAGS
2× USB 2.0 HS
MLB 6-PIN
PCIe2.0 (1 lane)
HADC (8 CHAN, 12-BIT)
Rev. PrF
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

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