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PDF ICS512 Data sheet ( Hoja de datos )

Número de pieza ICS512
Descripción PLL CLOCK MULTIPLIER
Fabricantes IDT 
Logotipo IDT Logotipo



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LOCO™ PLL CLOCK MULTIPLIER
DATASHEET
ICS512
Description
Features
The ICS512 is the most cost effective way to generate
a high-quality, high frequency clock output and a
reference clock from a lower frequency crystal or clock
input. The name LOCO stands for Low Cost Oscillator,
as it is designed to replace crystal oscillators in most
electronic systems. Using Phase-Locked-Loop (PLL)
techniques, the device uses a standard fundamental
mode, inexpensive crystal to produce output clocks up
to 200 MHz. With a reference output, this chip plus an
inexpensive crystal can replace two oscillators
Stored in the chip’s ROM is the ability to generate nine
different multiplication factors, allowing one chip to
output many common frequencies (see table on page
2).
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined or guaranteed.
For applications which require defined input to output
skew, use the ICS570B.
Block Diagram
Packaged as 8-pin SOIC or die
Pb (lead ) free package
Upgrade of popular ICS502 with:
— changed multiplier table
— higher operating frequncies
Zero ppm multiplication error
Easy to cascade with other 5xx series
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Output clock frequencies up to 200 MHz
Compatible with all popular CPUs
Duty cycle of 45/55 up to 200 MHz
Mask option for nine selectable frequencies
Operating voltages of 3.0 to 5.5 V
Industrial temperature version available
Advanced, low power CMOS process
VDD
S1, S0
X1/ICLK
Crystal or
Clock input
X2
2
Crystal
Oscillator
Optional crystal
capacitors
PLL Clock
Synthesis
and Control
Circuitry
GND
CLK
REF
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER
1
ICS512
REV H 051310

1 page




ICS512 pdf
ICS512
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
DC Electrical Characteristics
VDD=3.3 V ±5% , Ambient temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol Conditions
Min. Typ. Max. Units
Operating Voltage
VDD
3 5.5 V
Input High Voltage, ICLK only
VIH ICLK (pin 1)
(VDD/2)+1 VDD/2
V
Input Low Voltage, ICLK only
VIL ICLK (pin 1)
VDD/2 (VDD/2)-1 V
Input High Voltage
VIH S0, S1
VDD-0.5
V
Input Low Voltage
VIL S0, S1
0.5 V
Output High Voltage, CMOS high VOH IOH = -8 mA
VDD-0.4
V
Output High Voltage
VOH IOH = -12 mA
2.4
V
Output Low Voltage
VOL IOL = 12 mA
0.4 V
IDD Operating Supply Current,
No load, 100 MHz
9
mA
20 MHz crystal
Short Circuit Current
CLK output
+70 mA
Input Capacitance, S1, S0
Pins 6, 7
4 pF
AC Electrical Characteristics
VDD=3.3 V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol Conditions
Min. Typ. Max. Units
Input Frequency, crystal input
Input Frequency, clock input
Output Frequency, VDD = 4.5 to 5.5 V
FIN
FIN
FOUT
0 to +70°C
-40 to +85°C
5
2
14
14
27 MHz
50 MHz
200 MHz
160 MHz
Output Frequency, VDD = 3.0 to 3.6 V FOUT 0 to +70°C
-40 to +85°C
14
14
160 MHz
145 MHz
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Absolute Clock Period Jitter
tOR 0.8 to 2.0 V
tOF 2.0 to 8.0V
tOD at VDD/2
tja Deviation from
mean
1
1
45 49-51 55
+200
ns
ns
%
ps
One Sigma Clock Period Jitter
tjs
80 ps
Note: The phase relationship between intput and output clocks can change at power up. For a fixed phase
relationship, see the ICS570 or the ICS527.
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER
5
ICS512
REV H 051310

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