PDF VSC7106 Data sheet ( Hoja de datos )

Número de pieza	VSC7106
Descripción	1.0625 Gbit/sec Transmitter/Receiver Chipset
Fabricantes	Vitesse Semiconductor
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No Preview Available ! VITESSE VSC7105/7106 Data Sheet 1.0625 Gbit/sec Transmitter/Receiver Chipset for Fibre Channel or Proprietary Serial Links Features • ANSI X3T11 Fibre Channel Compatible at 1.0625 Gbit/s • On-chip Fully Monolithic Clock Recovery and Clock Multiplication Circuits Require No External Components • On Chip Clock Multiplication Relieves Sys- tem of High Speed Clock Generation • Single +3.3V Supply Operation • Dual Receiver Serial Inputs and Transmitter Outputs for Loopback and Multiple Link Applications • Selectable 10 or 20 bit TTL Compatible Parallel Interface • High Sensitivity Differential Receiver Suitable for both Coaxial and Optical Link Applications General Description The VSC7105/VSC7106 chipset is compatible with the ANSI X3T11 Fibre Channel Standard. Fibre Chan- nel is a high speed communication channel standardized by ANSI for mapping upper layer protocols (ULP) such as SCSI, IP, and HIPPI. Fibre Channel can then provide a channel over which concurrent communication of all ULP’s may exist on a single interconnect between workstations, mainframes, and supercomputers, and for connection to mass storage devices and other peripherals. The Fibre Channel physical layer is also ideal for building cost effective, very high speed point-to-point communications links. This chipset implements the Fibre Channel electrical transceiver physical layer for 1.0625 Gb/s operation. At 1.0625 Gb/s, Fibre Channel delivers 100 MByte/s of data bandwidth over a single cable. This bandwidth equals or exceeds most bus bandwidths. This chipset performs the high speed serialization and de-serialization function that makes bus-bandwidth, serial communication possible. This chipset can drive electrical cables directly or interface with optical modules. System Block Diagram Controller I/O Bus Bus Logic Transmit FIFO’s Receive FIFO’s VITESSE VSC7107 ENDEC VITESSE VSC7105 TX VITESSE VSC7106 RX 1.0625 Gb/s Serial Data Over Copper or Optical Cable VITESSE VSC7106 RX VITESSE VSC7105 TX G52079-0 Rev. 2.7 ® VITESSE Semiconductor Cororation Page 1 1 page VITESSE VSC7105/7106 Data Sheet 1.0625 Gbit/sec Transmitter/Receiver Chipset for Fibre Channel or Proprietary Serial Links R10:19. R00:09 are held HIGH in this mode. The functional block diagrams for operation in 20-bit or 10-bit modes are shown in Figure 4 and Figure 5 respectively. Word synchronization is enabled in the VSC7106 by tying the SYNCEN pin to VDD. When synchronization is enabled, the VSC7106 constantly examines the serial data for the presence of the Fibre Channel “Sync” char- acter. This pattern is “0011111010” and is referred to as a K28.5 character with negative beginning disparity. The K28.5 character is not a normal data character, but a special character deﬁned speciﬁcally for synchroniza- tion by Fibre Channel. Improper alignment occurs when a K28.5 straddles a 10 bit boundary or when a K28.5 is in the wrong 10-bit position of a half-word. When an improperly aligned sync character is encountered in 20-bit mode, the internal divider which produces RCLK and RCLKN is stalled in such a manner that the sync charac- ter is aligned in the R00:09 output ﬁeld. This results in proper character and half-word alignment. In 10-bit mode, proper alignment is established when the K28.5 does not straddle a 10-bit character boundary, and appears in a character that is clocked out on the falling edge of RCLKN. Half-word synchronization is still rele- vant in 10-bit mode. When the parallel data alignment changes in response to a sync pattern, some data which would have been presented on the parallel output port will be lost. The detection of the sync character is pipelined. Depending on the required new output phase, the sync character itself may be destroyed by the synchronization operation. Nonetheless, data following the sync character will be correctly aligned. Thus if downstream logic requires detection of the sync character (for example, to accomplish ordered set alignment) then more than one sync character must be transmitted in order to guarantee that one will be forwarded out of the VSC7106 incorrupt- ible. Fibre Channel compliant systems requires the receipt of a minimum of three ordered sets for word syn- chronization. Ordered sets are special Fibre Channel transmission words that have the K28.5 sync character as the ﬁrst character received. The ﬁrst of these ordered sets will cause resynchronization in the VSC7106. The subsequent two ordered sets will be correctly aligned when they are received. In systems where synchronization is undesired, tying SYNCEN to GND will disable the sync function, and the data will be unframed. On encountering a sync pattern, a pulse is generated on the SYNC output to inform the user that realign- ment of the parallel data ﬁeld may have occurred. The SYNC pulse is presented one cycle in advance of the actual K28.5 character, and has a duration equal to the data. When operating the VSC7106 in 20-bit mode, the SYNC pulse spans one period of RCLK. In 10-bit mode, the pulse is HIGH for half of an RCLK period. Func- tional waveforms for synchronization in both modes are given in Figure 6 and Figure 7. Figure 6 shows the case when a sync character is detected and no phase adjustment is necessary. It illustrates the position of the SYNC pulse in relation to the sync character. Figure 7 shows the case where the K28.5 is detected, but out of alignment and a change in RCLK and the output data is required. Note that the VSC7106 always stretches the RCLK so it will never create a clock sliver on resynchronization. G52079-0 Rev. 2.7 ® VITESSE Semiconductor Cororation Page 5 5 Page VITESSE VSC7105/7106 Data Sheet 1.0625 Gbit/sec Transmitter/Receiver Chipset for Fibre Channel or Proprietary Serial Links Table 2: VSC7105 AC Characteristics Parameters T0 T1 T2 T3 T4 T5 Description REFCLK rise to TCLK fall and TCLKN rise REFCLK rise to TCLK rise and TCLKN fall Data setup w.r.t. REFCLK Data hold w.r.t. REFCLK Data setup w.r.t. TCLK/ TCLKN Data hold w.r.t TCLK/TCLKN Min 1.0 1.0 1.0 5.0 5.0 1.0 TCR,TCF TCLK rise and fall time TSDR,TSDF Serial data rise and fall time T6 TCLK to TCLKN skew TDC TCLK, TCLKN duty cycle Transmitter Output Jitter Allocation TJ (RMS) Serial data output random jitter (RMS) TDJ Serial data output deterministic jitter (p-p) — — — 45 — — Max Units 4.0 ns — Conditions 4.0 ns — — ns — — ns — — ns Derived from Data setup to REFCLK and REFCLK to TCLK/TCLKN delay — ns Derived from Data hold from REFCLK and REFCLK to TCLK/TCLKN delay 5.0 ns 0.8V to 2.0V, tested on a sample basis Refer to TTL Rise/Fall Time vs. Loading 300 ps 20% to 80%, tested on a sample basis +/-1 ns Tested on a sample basis 55 % — 20 ps RMS, tested on a sample basis (refer to Figure 13) 100 ps Peak to peak, tested on a sample basis (refer to Figure 13) G52079-0 Rev. 2.7 ® VITESSE Semiconductor Cororation Page 11 11 Page

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