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PDF AD8450 Data sheet ( Hoja de datos )
| Número de pieza | AD8450 | |
| Descripción | Precision Analog Front End and Controller | |
| Fabricantes | Analog Devices | |
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Data Sheet
Precision Analog Front End and Controller
for Battery Test/Formation Systems
AD8450
FEATURES
GENERAL DESCRIPTION
Integrated constant current and voltage modes with
automatic switchover
Charge and discharge modes
Precision voltage and current measurement
Integrated precision control feedback blocks
Precision interface to PWM or linear power converters
Programmable gain settings
Current sense gains: 26, 66, 133, and 200
Voltage sense gains: 0.2, 0.27, 0.4, and 0.8
Programmable OVP and OCP fault detection
Current sharing and balancing
Excellent ac and dc performance
Maximum offset voltage drift: 0.6 µV/°C
Maximum gain drift: 3 ppm/°C
Low current sense amplifier input voltage noise: ≤9 nV/√Hz
Current sense CMRR: 126 dB minimum (gain = 200)
TTL compliant logic
The AD8450 is a precision analog front end and controller for
testing and monitoring battery cells. A precision programmable
gain instrumentation amplifier (PGIA) measures the battery
charge/discharge current, and a programmable gain difference
amplifier (PGDA) measures the battery voltage (see Figure 1).
Internal laser trimmed resistor networks set the gains for the
PGIA and the PGDA, optimizing the performance of the
AD8450 over the rated temperature range. PGIA gains are 26,
66, 133, and 200. PGDA gains are 0.2, 0.27, 0.4, and 0.8.
Voltages at the ISET and VSET inputs set the desired constant
current (CC) and constant voltage (CV) values. CC to CV
switching is automatic and transparent to the system.
A TTL logic level input, MODE, selects the charge or discharge
mode (high for charge, low for discharge). An analog output,
VCTRL, interfaces directly with the Analog Devices, Inc.,
ADP1972 PWM controller.
APPLICATIONS
Battery cell formation and testing
Battery module testing
The AD8450 includes resistor programmable overvoltage and
overcurrent detection and current sharing circuitry. Current
sharing is used to balance the output current of multiple
bridged channels.
The AD8450 simplifies designs by providing excellent accuracy,
performance over temperature, flexibility with functionality,
and overall reliability in a space-saving package. The AD8450 is
available in an 80-lead, 14 mm × 14 mm × 1 mm LQFP package
and is rated for an operating temperature of −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
ISREFH/
IVE0/
ISREFL ISMEA ISET IVE1
VINT
ISVP
ISVN
MODE
BVPx
BVNx
GAIN
NETWORK
AND MUX
26, 66,
133, 200
CURRENT
SENSE PGIA
GAIN
NETWORK
VOLTAGE
SENSE PGDA
0.2, 0.27,
0.4, 0.8
CONSTANT
CURRENT LOOP
FILTER
(CHARGE/
DISCHARGE)
SWITCHING
CONSTANT
VOLTAGE LOOP
FILTER
AD8450
CURRENT
SHARING
1×
VOLTAGE
REFERENCE
CSH
IMAX
VCLP
VCTRL
VCLN
VREF
FAULT
DETECTION
FAULT
BVREFH/
BVREFL
BVMEA
VSET VVE0/
VVE1
Figure 1.
VVP0 VSETBF VINT OVPS/ OCPS/
OVPR OCPR
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
Parameter
Small Signal −3 dB Bandwidth
Gain = 0.2
Gain = 0.27
Gain = 0.4
Gain = 0.8
Slew Rate
CONSTANT CURRENT AND CONSTANT
VOLTAGE LOOP FILTER AMPLIFIERS
Offset Voltage
Offset Voltage Drift
Input Bias Current
Over Temperature
Input Common-Mode Voltage Range
Output Voltage Swing
Over Temperature
Closed-Loop Output Impedance
Capacitive Load Drive
Source Short-Circuit Current
Sink Short-Circuit Current
Open-Loop Gain
CMRR
PSRR
Voltage Noise
Voltage Noise, Peak-to-Peak
Current Noise
Current Noise, Peak-to-Peak
Small Signal Gain Bandwidth Product
Slew Rate
CC to CV Transition Time
UNCOMMITTED OP AMP
Offset Voltage
Offset Voltage Drift
Input Bias Current
Over Temperature
Input Common-Mode Voltage Range
Output Voltage Swing
Over Temperature
Closed-Loop Output Impedance
Capacitive Load Drive
Short-Circuit Current
Open-Loop Gain
CMRR
PSRR
Voltage Noise
Voltage Noise, Peak-to-Peak
Current Noise
Current Noise, Peak-to-Peak
Small Signal Gain Bandwidth Product
Slew Rate
Test Conditions/Comments
TA = TMIN to TMAX
TA = TMIN to TMAX
VVCLN = AVEE + 1 V, VVCLP = AVCC − 1 V
TA = TMIN to TMAX
ΔVCM = 10 V
ΔVS = 20 V
f = 1 kHz
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 0.1 Hz to 10 Hz
ΔVVINT = 10 V
TA = TMIN to TMAX
TA = TMIN to TMAX
TA = TMIN to TMAX
RL = 2 kΩ
ΔVCM = 10 V
ΔVS = 20 V
f = 1 kHz
f = 0.1 Hz to 10 Hz
f = 1 kHz
f = 0.1 Hz to 10 Hz
ΔVOAVO = 10 V
Min Typ
420
730
940
1000
0.8
−5
−5
AVEE + 1.5
AVEE + 1.5
AVEE + 1.7
0.01
1
40
140
10
0.3
80
5
3
1
1.5
−5
−5
AVEE + 1.5
AVEE + 1.5
AVEE + 1.7
0.01
40
140
10
0.3
80
5
3
1
AD8450
Max Unit
kHz
kHz
kHz
kHz
V/µs
150
0.6
+5
+5
AVCC − 1.8
AVCC − 1
AVCC − 1
1000
100
100
µV
µV/°C
nA
nA
V
V
V
Ω
pF
mA
mA
dB
dB
dB
nV/√Hz
µV p-p
fA/√Hz
pA p-p
MHz
V/μs
µs
150
0.6
+5
+5
AVCC − 1.8
AVCC − 1.5
AVCC − 1.5
1000
100
100
µV
µV/°C
nA
nA
V
V
V
Ω
pF
mA
dB
dB
dB
nV/√Hz
µV p-p
fA/√Hz
pA p-p
MHz
V/µs
Rev. B | Page 5 of 41
5 Page 
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, AVCC = +25 V, AVEE = −5 V, RL = ∞, unless otherwise noted.
PGIA CHARACTERISTICS
30
VALID FOR ALL GAINS
25
20
15
10
5
0
–5
AVCC = +25V
AVEE = –5V
–10
–10 –5
0
5 10 15 20 25 30
OUTPUT VOLTAGE (V)
Figure 3. Input Common-Mode Voltage vs. Output Voltage
for AVCC = +25 V and AVEE = −5 V
15
10
GAIN = 200
5
0
GAIN = 26
–5
–10
AVCC = +25V
AVEE = –5V
–15
–35 –30 –25 –20 –15 –10 –5 0
5 10 15 20 25 30 35 40 45
INPUT VOLTAGE (V)
Figure 4. Input Overvoltage Performance
for AVCC = +25 V and AVEE = −5 V
17.0
VALID FOR ALL GAINS
16.8
16.6
16.4
16.2 AVCC = +15V
AVEE = –15V
16.0
AVCC = +25V
15.8 AVEE = –5V
15.6
15.4
15.2
15.0
–15
–10
–5
0
5 10 15 20 25
INPUT COMMON-MODE VOLTAGE (V)
Figure 5. Input Bias Current vs. Input Common-Mode Voltage
AD8450
20
VALID FOR ALL GAINS
15
10
5
0
–5
–10
–15
AVCC = +15V
AVEE = –15V
–20
–20 –15 –10
–5
0
5 10 15 20
OUTPUT VOLTAGE (V)
Figure 6. Input Common-Mode Voltage vs. Output Voltage
for AVCC = +15 V and AVEE = −15 V
15
AVCC = +15V
AVEE = –15V
10
5
GAIN = 200
0
GAIN = 26
–5
–10
–15
–45–40–35–30–25–20–15–10 –5 0 5 10 15 20 25 30 35 40 45
INPUT VOLTAGE (V)
Figure 7. Input Overvoltage Performance
for AVCC = +15 V and AVEE = −15 V
20
19
18
17
+IB
16
–IB
15
14
13
12
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
Figure 8. Input Bias Current vs. Temperature
Rev. B | Page 11 of 41
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD8450.PDF ] | |
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