PDF AD6676 Data sheet ( Hoja de datos )

Número de pieza	AD6676
Descripción	Wideband IF Receiver Subsystem
Fabricantes	Analog Devices
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Data Sheet Wideband IF Receiver Subsystem AD6676 FEATURES APPLICATIONS High instantaneous dynamic range Wideband cellular infrastructure equipment and repeaters Noise figure (NF) as low as 13 dB Point-to-point microwave equipment Noise spectral density (NSD) as low as −159 dBFS/Hz Instrumentation IIP3 up to 36.9 dBm with spurious tones <−99 dBFS Spectrum and communication analyzers Tunable band-pass Σ-Δ analog-to-digital converter (ADC) Software defined radio 20 MHz to 160 MHz signal bandwidth 70 MHz to 450 MHz IF center frequency Configurable input full-scale level of −2 dBm to −14 dBm Easy to drive resistive IF input Gain flatness of 1 dB with under 0.5 dB out-of-band peaking Alias rejection greater than 50 dB 2.0 GSPS to 3.2 GSPS ADC clock rate On-chip PLL clock multiplier 16-bit I/Q rate up to 266 MSPS On-chip digital signal processing NCO and quadrature digital downconverter (QDDC) GENERAL DESCRIPTION The AD66761 is a highly integrated IF subsystem that can digitize radio frequency (RF) bands up to 160 MHz in width centered on an intermediate frequency (IF) of 70 MHz to 450 MHz. Unlike traditional Nyquist IF sampling ADCs, the AD6676 relies on a tunable band-pass Σ-Δ ADC with a high oversampling ratio to eliminate the need for band specific IF SAW filters and gain stages, resulting in significant simplification of the wideband radio receiver architecture. On-chip quadrature digital downconversion followed by selectable decimation filters Selectable decimation factor of 12, 16, 24, and 32 reduces the complex data rate to a manageable rate between Automatic gain control (AGC) support 62.5 MSPS to 266.7 MSPS. The 16-bit complex output data is On-chip attenuator with 27 dB span in 1 dB steps transferred to the host via a single or dual lane JESD204B interface Fast attenuator control via configurable AGC data port supporting line rates of up to 5.333 Gbps. Peak detection flags with programmable thresholds Single or dual lane, JESD204B capable Low power consumption: 1.20 W 1.1 V and 2.5 V supply voltage TDD power saving up to 60% 4.3 mm × 5.0 mm WLCSP FUNCTIONAL BLOCK DIAGRAM VSS2IN VSS2OUT VDD2NV AGC4, AGC3 AGC2, AGC1 VDDIO RESETB VIN+ VIN– L+ L– –2.0V REG 27dB ATTENUATOR (1dB STEPS) BAND-PASS Σ-Δ ADC AGC SUPPORT QDDC + NCO I Q I Mx M = 12, Q 16, 24, 32 SPI CSB SCLK SDIO SDO VDDHSI SERDOUT0+ SERDOUT0– SERDOUT1+ SERDOUT1– CLOCK SYNTHESIZER CLOCK GENERATION JESD204B SUBCLASS 1 CONTROL AD6676 SYNCINB± SYSREF± VDDQ VDDC CLK+ CLK– VDD2 VDDL VDD1 VSSA VDDD VSSD Figure 1. 1 This product is protected by U.S. and international patents. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet AD6676 SPECIFICATIONS VDD1 = VDDL = VDDC = VDDQ = 1.1 V, VDDD = VDDHSI = 1.1 V, VDD2 = 2.5 V, VDDIO = 1.8 V, FIF = 250 MHz, BW = 75 MHz, FADC = 3.2 GHz, attenuator = 0 dB, L± (inductor values) = 19 nH, maximum PIN_0dBFS setting with IDAC1FS = 4 mA, fDATA_IQ = 200 MSPS, shuffler enabled (every clock cycle) with default threshold of 5, unless otherwise noted. Table 1. Parameter SYSTEM DYNAMIC PERFORMANCE Full-Scale Input Power Level (PIN_0dBFS)1 Maximum Continuous Wave (CW) Input Power2 Noise Figure (NF) Worst In-Band Noise Spectral Density Noise Figure at IF Center (NF) In-Band Noise Spectral Density (NSD) Input Second-Order Intercept (IIP2) Second-Order Intermodulation Distortion (IMD) (IMD2) Input Third-Order Intercept (IIP3) Third-Order IMD (IMD3) Worst In-Band Spur for Swept CW Tone In-Band Noise Gain Variation IF INPUT (VIN±) Input Span 0 dB Attenuator Setting 12 dB Attenuator Setting Common-Mode Input Voltage Differential Input Impedance Common-Mode Input Impedance Full-Scale Input Power Adjustment (PIN_0dBFS) DIGITAL STEP ATTENUATOR (VIN±) Attenuation Range Step Size Input Return Loss Input Return Loss Variation vs. Attenuator Setting CLOCK INPUT (CLK±) Clock Synthesizer Disabled Frequency Range Amplitude Range Differential Input Impedance Common Mode Impedance Input Return Loss Common-Mode Voltage Clock Synthesizer Enabled Frequency Range3 Amplitude Range CLK+ Input Impedance Minimum Slew Rate Common-Mode Voltage Temperature Full Full Full Full Full Full Full 25°C 25°C Full Full Full Full Full Full 25°C 25°C 25°C 25°C Full Full 25°C 25°C Test Conditions/Comments Min No signal and measured Over a 5 MHz bandwidth No signal and measured Over a 5 MHz bandwidth −6 dBFS tones See Table 20 −8 dBFS tones −8 dBFS tones −2 dBFS tone −10 dBFS tone −2 dBFS tone No CW tone −2 0 dBFS Self biased IDAC1FS span of 1 mA to 4 mA At 3 GHz At 3 GHz With 1:2 balun Self biased Single-ended into CLK+ 2.0 0.4 10 0.4 Self biased Typ −2 −1 17 −155 13 −159 60 −68.3 36.9 −95 −99 −109.6 −75.5 −78.5 0.5 0.48 1.92 1.0 60\|\|2 3.5 12 27 1 20 2 0.8 86\|\|0.3 700\|\|0.8 15 0.70 0.8 1.4\|\|1.0 12 0.55 Max Unit dBm dBFS −152.5 dB dBFS/Hz dB dBFS/Hz dBm dBc −84.2 −93.5 −73.7 −76.5 dBm dBc dBFS dBFS dBFS dBFS dB V p-p V p-p V Ω\|\|pF kΩ dB dB dB dB dB 3.2 GHz 2.0 V p-p Ω\|\|pF Ω\|\|pF dB V 320 MHz 1.1 V p-p kΩ\|\|pF V/µs V Rev. A \| Page 5 of 90 5 Page Data Sheet Pin No. Power Supplies G8 J1, J2 H3 to H5, J3 to J5 F4, F5, G2 to G5, H2 A1 C2, D1, D2 D4, D5 A2, A4, B2, B3, B5, C3, C4, C6, D3, D7 A5, B6, B7, E7, E8 A3, A8, B4, C5, C7, D6, D8, E1 to E6, F1 to F3, F8 Negative Voltage Regulator F7 G7 F6 Mnemonic VDDIO VDDHSI VDDD VSSD VDDQ VDDC VDDL VDD1 VDD2 VSSA VDD2NV VSS2OUT VSS2IN AD6676 Description Digital Supply Input for CMOS Input/Outputs (1.8 V to 2.5 V). Digital 1.1 V Supply Input for the High Speed Serial Interface. Digital 1.1 V Supply Input. Digital Supply Return. Analog 1.1 V Supply Input for the CLK Synthesizer Charge Pump and Dividers. Analog 1.1 V Supply Input for the CLK Synthesizer VCO. Analog 1.1 V Supply Input for the ADC. Analog 1.1 V Supply Input for the ADC. Analog 2.5 V Supply Input. Analog Supply Return. Analog 2.5 V Supply Input. Internal −2.0 V Supply Output. Connect this pin to VSS2IN. Analog −2.0 V Supply Input. Connect this pin to VSS2OUT. Rev. A \| Page 11 of 90 11 Page

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