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PDF HX8352-B01 Data sheet ( Hoja de datos )
| Número de pieza | HX8352-B01 | |
| Descripción | TFT Mobile Single Chip Driver | |
| Fabricantes | Himax | |
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DATA SHEET
( DOC No. HX8352-B01-DS )
HX8352-B01(T)
240RGB x 432 dot, 262K color,
with internal GRAM,
TFT Mobile Single Chip Driver
Preliminary version 01 November, 2009
1 page  
HX8352-B01(T)
240RGB x 432 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Figures
November, 2008
Figure 5.1 Register read/write timing in parallel bus system interface (for I80 series MPU) ............ 33
Figure 5.2 GRAM read/write timing in parallel bus system interface (for I80 series MPU)............... 34
Figure 5.3 Example of I80- system 18-bit parallel bus interface ....................................................... 37
Figure 5.4 Input data bus and GRAM data mapping in 18-bit bus system interface with 18 bit-data
input (“BS3, BS2, BS1, BS0”=”1010” or “1000”) ........................................................................ 37
Figure 5.5 Example of I80 system 16-bit parallel bus interface type I .............................................. 38
Figure 5.6 Example of I80 system 16-bit parallel bus interface type II ............................................. 38
Figure 5.7 Input data bus and GRAM data mapping in 16-bit bus system interface with 12 bit-data
input (R17H=03h and “BS3, BS2, BS1, BS0”=”0000”) .............................................................. 39
Figure 5.8 Input data bus and GRAM data mapping in 16-bit bus system interface with 12 bit-data
input (R17H=04h and “BS3, BS2, BS1, BS0”=”0000”) .............................................................. 39
Figure 5.9 Input data bus and GRAM data mapping in 16-bit bus system interface with 16 bit-data
input (R17H=05h and “BS3, BS2, BS1, BS0”=”0000”) .............................................................. 39
Figure 5.10 Input data bus and GRAM data mapping in 16-bit bus system interface with 18(12+6)
bit-data input (R17H=06h and “BS3, BS2, BS1, BS0”=”0000”) ..................錯誤! 尚未定義書籤。
Figure 5.11 Input data bus and GRAM data mapping in 16-bit bus system interface with 18(16+2)
bit-data input (R17H=07h and “BS3,BS2, BS1, BS0”=”0000”) .................................................. 39
Figure 5.12 Input data bus and GRAM data mapping in 16-bit bus system interface with 12 bit-data
input (R17H=03h and “BS3, BS2, BS1, BS0”=”0010”) .............................................................. 40
Figure 5.13 Input data bus and GRAM data mapping in 16-bit bus system interface with 12 bit-data
input (R17H=04h and “BS3, BS2, BS1, BS0”=”0010”) .............................................................. 40
Figure 5.14 Input data bus and GRAM data mapping in 16-bit bus system interface with 16 bit-data
input (R17H=05h and “BS3, BS2, BS1, BS0”=”0010”) .............................................................. 40
Figure 5.15 Input data bus and GRAM data mapping in 16-bit bus system interface with 18(12+6)
bit-data input (R17H=06h and “BS3, BS2, BS1, BS0”=”0010”) ................................................. 40
Figure 5.16 Input data bus and GRAM data mapping in 16-bit bus system interface with 18(16+2)
bit-data input (R17H=07h and “BS3, BS2, BS1, BS0”=”0010”) ................................................. 41
Figure 5.17 Example of I80 system 9-bit parallel bus interface type I .............................................. 42
Figure 5.18 Example of I80 system 9-bit parallel bus interface type II ............................................. 42
Figure 5.19 Input data bus and GRAM data mapping in 9-bit bus system interface with 18 bit-data
input (R17H=06h and “BS3, BS2, BS1, BS0”=”1001”) .............................................................. 43
Figure 5.20 Input data bus and GRAM data mapping in 9-bit bus system interface with 18 bit-data
input (R17H=06h and “BS3, BS2, BS1, BS0”=”1011”) .............................................................. 43
Figure 5.21 Example of I80-system 8-bit parallel bus interface type I .............................................. 44
Figure 5.22 Example of I80-system 8-bit parallel bus interface type II ............................................. 44
Figure 5.23 Input data bus and GRAM data mapping in 8-bit bus system interface with 12 bit-data
input (R17H=03h and“BS3, BS2, BS1, BS0”=”0001”) ............................................................... 45
Figure 5.24 Input data bus and GRAM data mapping in 8-bit bus system interface with 16 bit-data
input (R17H=05h and “BS3, BS2, BS1, BS0”=”0001”) .............................................................. 45
Figure 5.25 Input data bus and GRAM data mapping in 8-bit bus system interface with 18 bit-data
input (R17H=06h and “BS3, BS2, BS1, BS0”=”0001”) .............................................................. 45
Figure 5.26 Input data bus and GRAM data mapping in 8-bit bus system interface with 12 bit-data
input (R17H=03h and“BS3, BS2, BS1, BS0”=”0011”) ............................................................... 46
Figure 5.27 Input data bus and GRAM data mapping in 8-bit bus system interface with 16 bit-data
input (R17H=05h and “BS3, BS2, BS1, BS0”=”0011”) .............................................................. 46
Figure 5.28 Input data bus and GRAM data mapping in 8-bit bus system interface with 18 bit-data
input (R17H=06h and “BS3, BS2, BS1, BS0”=”0011”) .............................................................. 46
Figure 5.29 Index register read/write timing in 3-wire serial bus system interface ........................... 49
Figure 5.30 Data write timing in 3-wire serial bus system interface.................................................. 50
Figure 5.31 Index register write timing in 4-wire serial bus system interface ................................... 50
Figure 5.32 Data write timing in 4-wire serial bus system interface.................................................. 51
Figure 5.33 DOTCLK cycle ............................................................................................................... 52
Figure 5.34 RGB interface circuit input timing diagram .................................................................... 53
Figure 5.35 RGB mode timing diagram ............................................................................................ 54
Figure 5.36 RGB 18-bit/pixel on 6-bit data width .............................................................................. 57
Himax Confidential
-P.4-
This information contained herein is the exclusive
in whole or in part without prior written permission
property of
of Himax.
Himax
and
shall
not
be
distributed,
reproduced,
or
disclosed
November,
2008
5 Page 
HX8352-B01(T)
240RGB x 432 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver
List of Tables
November, 2008
Table 5.1 Input bus format selection of system interface circuit ....................................................... 32
Table 5.2 Data pin function for I80 series CPU ................................................................................. 33
Table 5.3 8-bit parallel interface type I GRAM write table ................................................................. 35
Table 5.4 16-bit parallel interface type I GRAM write table ............................................................... 35
Table 5.5 9-bit parallel interface type I GRAM write table ................................................................. 35
Table 5.6 18-bit parallel interface type I GRAM write table ............................................................... 35
Table 5.7 8-bit parallel interface type II GRAM write table ................................................................ 36
Table 5.8 16-bit parallel interface type II GRAM write table .............................................................. 36
Table 5.9 9-bit parallel interface set type II GRAM write table .......................................................... 36
Table 5.10 18-bit parallel interface type II GRAM write set table ...................................................... 36
Table 5.11 8-bit parallel interface type I GRAM read table................................................................ 47
Table 5.12 16-bit parallel interface type I GRAM read table ............................................................. 47
Table 5.13 9-bit parallel interface type I GRAM read table ............................................................... 47
Table 5.14 18-bit parallel interface type I GRAM read table ............................................................. 47
Table 5.15 8-bit parallel interface type II GRAM read table .............................................................. 48
Table 5.16 16-bit parallel interface type II GRAM read table ............................................................ 48
Table 5.17 9-bit parallel interface type II GRAM read table .............................................................. 48
Table 5.18 18-bit parallel interface type II GRAM read table ............................................................ 48
Table 5.19 Function of RS and R/W bit bus ...................................................................................... 49
Table 5.20 RGB interface bus width set table ................................................................................... 55
Table 5.21 Meaning of pixel information for main colors on RGB interface ...................................... 56
Table 5.22 List of supported MDDI packet ........................................................................................ 64
Table 5.23 GPIO control related register........................................................................................... 75
Table 5.24 Operation mode list ......................................................................................................... 79
Table 6.1 GRAM address for display panel position (240 X 432) ..................................................... 94
Table 6.2 Address counter range ...................................................................................................... 95
Table 6.3 CASET and PASET control for physical column/page pointers ........................................ 96
Table 6.4 Rules for updating GRAM order ........................................................................................ 97
Table 6.5 Address direction settings ................................................................................................. 98
Table 6.6 GRAM X address and display panel position (240RGBx432 dot)................................... 101
Table 6.7 GRAM address and display panel position (GS=L, 240RGBx432 dot)........................... 102
Table 6.8 GRAM address and display panel position (GS=H , 240RGBx432 dot) ......................... 102
Table 6.9 ISC[3:0] bits definition...................................................................................................... 104
Table 7.1 Gamma-adjustment registers ...........................................................................................112
Table 7.2 Offset adjustment 0~5 ......................................................................................................114
Table 7.3 Center adjustment ............................................................................................................114
Table 7.4 Voltage calculation formula for VinP/N 0..........................................................................115
Table 7.5 Voltage calculation formula for VinP/N 1..........................................................................116
Table 7.6 Voltage calculation formula for VinP/N 2..........................................................................117
Table 7.7 Voltage calculation formula for VinP/N 3..........................................................................118
Table 7.8 Voltage calculation formula for VinP/N 4......................................................................... 120
Table 7.9 Voltage calculation formula for VinP/N 5......................................................................... 121
Table 7.10 Voltage calculation formula for VinP/N 6....................................................................... 122
Table 7.11 Voltage calculation formula for VinP/N 7 ....................................................................... 123
Table 7.12 Voltage calculation formula for VinP/N 8....................................................................... 125
Table 7.13 Voltage calculation formula for VinP/N 9....................................................................... 126
Table 7.14 Voltage calculation formula for VinP/N 10..................................................................... 127
Table 7.15 Voltage calculation formula for VinP/N 11..................................................................... 128
Table 7.16 Voltage calculation formula for VinP/N 12..................................................................... 129
Table 7.17 Voltage calculation formula of 64-grayscale voltage (positive polarity) ........................ 130
Table 7.18 Voltage calculation formula of grayscale voltage V2~V7 and V56~V61 ....................... 130
Table 7.19 Voltage calculation formula of 64-grayscale voltage (negative polarity) ....................... 131
Table 7.20 Voltage calculation formula of grayscale voltage V2~V7 and V56~V61 ....................... 131
Table 7.21 DGLUT for red color (1)................................................................................................. 134
Table 7.22 DGLUT for red color (2)................................................................................................. 135
Himax Confidential
-P.10-
This information contained herein is the exclusive
in whole or in part without prior written permission
property of
of Himax.
Himax
and
shall
not
be
distributed,
reproduced,
or
disclosed
November,
2008
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HX8352-B01.PDF ] | |
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